公开(公告)号：US20240023324A1

公开(公告)日：2024-01-18

申请号：US18446506

申请日：2023-08-09

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Chao LIN

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B12/488 ,  H10B12/05 ,  H10B12/482 ,  H01L23/5226 ,  H01L23/5283

Abstract: A three-dimensional semiconductor structure and a method for forming the same are provided. The method includes the following operations. A stack structure in a source region and a drain region is etched to form a plurality of parallel first trenches extending in the first direction in the stack structure in the source region and the drain region, in which a plurality of semiconductor layers retained in the channel region serve as a plurality of channel body layers. The channel body layers extend in a second direction, and each includes a plurality of channel areas arranged in the second direction. A through via is formed in an end of the channel body layers in the second direction and penetrates the end. A conductive material is filled in the through via to form a grounded conductive plug.

公开(公告)号：US20230013735A1

公开(公告)日：2023-01-19

申请号：US17945113

申请日：2022-09-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Chao LIN

IPC: H01L27/108

Abstract: Embodiments relate to a semiconductor structure and a fabrication method thereof. The semiconductor structure has an array region and a peripheral region, and includes: a semiconductor substrate; a memory array structure positioned above the semiconductor substrate in the array region; a peripheral circuit structure positioned above the semiconductor substrate in the peripheral region; and a conductive connection structure positioned in the semiconductor substrate to electrically connect the memory array structure and the peripheral circuit structure. The semiconductor structure and the fabrication method thereof can effectively improve performance of a memory device.

公开(公告)号：US20240047558A1

公开(公告)日：2024-02-08

申请号：US18150850

申请日：2023-01-06

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Chao LIN

IPC: H01L29/66 ,  H10B12/00 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66742 ,  H01L29/66439 ,  H10B12/01 ,  H01L29/0642 ,  H01L29/66553 ,  H01L29/42384

Abstract: A method for forming a semiconductor structure is provided. The method includes: providing a base, the base including a first area and second areas located outside the first area, the first area including stack structures and isolation trenches alternately arranged in a first direction, the first direction being any direction in a plane where the base is located; performing ion implantation on sidewalls of the stack structure in the first direction, so as to form an active virtual connecting layer extending in the first direction and partially located in the isolation trenches; and forming a gate structure on a surface of the active virtual connecting layer.

公开(公告)号：US20230389339A1

公开(公告)日：2023-11-30

申请号：US18169839

申请日：2023-02-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Chao LIN

IPC: H10B80/00 ,  H01L23/00

CPC classification number: H10B80/00 ,  H01L24/02 ,  H01L24/80 ,  H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05181 ,  H01L2224/05169 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/05571 ,  H01L2224/80357 ,  H01L2224/8001 ,  H01L2224/80895 ,  H01L2224/06158 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor structure includes a first semiconductor layer and a second semiconductor layer bonded to each other. The first semiconductor layer includes a first redistribution line, and the first redistribution line has a first projection length on a bonding surface of the first semiconductor layer and the second semiconductor layer. The second semiconductor layer includes a second redistribution line, and the second redistribution line has a second projection length on the bonding surface. The first projection length is different from the second projection length. The first redistribution line is electrically connected to the second redistribution line. A method for forming the same is also provided.