公开(公告)号：US11935621B2

公开(公告)日：2024-03-19

申请号：US17448051

申请日：2021-09-19

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kai Tian ,  Yuxia Wang

IPC: H03K5/156 ,  G01R31/317 ,  G11C7/22 ,  G11C29/02 ,  H03K5/135

CPC classification number: G11C7/222 ,  G01R31/31727 ,  G11C29/023 ,  H03K5/135 ,  H03K5/1565

Abstract: A calibration circuit includes: a differential input circuit, configured to receive first and second oscillation signals, the first and second oscillation signals having the same frequency and opposite phases, duty cycle of the first oscillation signal and duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output first and internal signals; a comparison unit, connected to an output end of the differential input circuit and configured to compare duty cycle of the first internal signal and/or duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range.

公开(公告)号：US12088091B2

公开(公告)日：2024-09-10

申请号：US17810682

申请日：2022-07-05

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Ling Zhu ,  Kai Tian

IPC: H02H9/04 ,  H02H1/00

CPC classification number: H02H9/046 ,  H02H1/0007

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.

公开(公告)号：US20240030130A1

公开(公告)日：2024-01-25

申请号：US18095400

申请日：2023-01-10

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yingdong GUO ,  Kai Tian ,  Wei Jiang ,  Jing Xu

IPC: H01L23/525 ,  H01L23/62

CPC classification number: H01L23/5256 ,  H01L23/62

Abstract: Provided are an Electro Static Discharge (ESD) circuit and a memory. The ESD circuit includes: a detection circuit and multiple electrostatic discharge circuits. The detection circuit includes at least one sub-detection circuit connected between a first power end and a second power end. Each sub-detection circuit generates a sub-trigger signal based on a voltage change between the first power end and the second power end. The multiple electrostatic discharge circuits are connected between the first power end and the second power end. The multiple electrostatic discharge circuits are configured to be turned on according to the one or more sub-trigger signals.

公开(公告)号：US11881858B2

公开(公告)日：2024-01-23

申请号：US17502111

申请日：2021-10-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kai Tian ,  Yuxia Wang

IPC: H03K3/017 ,  G11C11/4076 ,  G11C7/22 ,  H03L7/08

CPC classification number: H03K3/017 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/08

Abstract: A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.

公开(公告)号：US11676642B2

公开(公告)日：2023-06-13

申请号：US17405107

申请日：2021-08-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Weibing Shang ,  Fengqin Zhang ,  Kangling Ji ,  Kai Tian ,  Xianjun Wu

IPC: G11C5/06 ,  G11C5/14 ,  G11C5/02 ,  H01L23/528

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C5/14 ,  H01L23/5286

Abstract: A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.

公开(公告)号：US11164849B2

公开(公告)日：2021-11-02

申请号：US17196926

申请日：2021-03-09

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kai Tian ,  Hongwen Li

IPC: H01L23/528 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.

公开(公告)号：US12218673B2

公开(公告)日：2025-02-04

申请号：US17822775

申请日：2022-08-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kai Tian ,  Ling Zhu

IPC: G11C21/00 ,  G11C11/4093 ,  H03K5/24

Abstract: A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.

公开(公告)号：US12081018B2

公开(公告)日：2024-09-03

申请号：US17807261

申请日：2022-06-16

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Ling Zhu ,  Kai Tian

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection network for a chip. The chip includes a first power supply pad, a second power supply pad, and a ground pad. The ESD protection network includes: a first ESD protection circuit, located between the first power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the first power supply pad; a second ESD protection circuit, located between the second power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the second power supply pad; and a third ESD protection circuit, configured to provide a discharge path for an electrostatic charge between the first power supply pad and the second power supply pad.

公开(公告)号：US11295804B2

公开(公告)日：2022-04-05

申请号：US17172319

申请日：2021-02-10

Applicant: Changxin Memory Technologies, Inc.

Inventor： Kai Tian

IPC: G11C11/4074

Abstract: The present invention provides an output circuit and a chip. The output circuit includes a first-stage circuit, a second-stage circuit, a third-stage circuit, and a fourth-stage circuit. The first-stage circuit is configured to read serial data in a memory and divide the serial data into first voltage signals each at a specified rate level; the second-stage circuit is configured to receive the first voltage signals, generate a plurality of second voltage signals; the third-stage circuit is configured to: allocate a transmission path to each of the second voltage signals according to a ZQ calibration signal; and the fourth-stage circuit includes a pull-up circuit and a pull-down circuit, each including thin-gate low-threshold NMOS transistors, and the fourth-stage circuit is configured to generate output voltage signals of the output circuit. By eliminating the limit on a minimum operating power supply voltage, different high-speed data output ports are compatible, thereby improving efficiency.

公开(公告)号：US12100946B2

公开(公告)日：2024-09-24

申请号：US17855845

申请日：2022-07-01

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Ling Zhu ,  Kai Tian

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0266 ,  H01L27/0292

Abstract: An electrostatic protection circuit includes: a monitoring unit, a discharge unit, and a controllable voltage dividing unit, where the monitoring unit is connected to at least one probe pad, a discharge unit and a controllable voltage dividing unit, and the monitoring unit is configured to generate a first trigger signal in response to that an electrostatic pulse is present on any probe pad; the discharge unit connected between the at least one probe pad and the ground pad, and configured to form, under control of the first trigger signal, at least one path for discharging electrostatic charges to the ground pad; and the controllable voltage dividing unit is connected to the discharge unit and is configured to share a part of voltage of the first trigger signal for the discharge unit.