公开(公告)号：US12047069B2

公开(公告)日：2024-07-23

申请号：US17849033

申请日：2022-06-24

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Keqin Huang ,  Kangling Ji

IPC: H03K19/17736 ,  G11C16/04 ,  H03K19/173

CPC classification number: H03K19/17744 ,  G11C16/0425 ,  H03K19/1737 ,  H03K19/1774

Abstract: A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where the first input end is configured to receive high level signal, the second input end is configured to receive low level signal, the control ends are connected to selection unit and the output end is connected to a serial wire, and the selection unit is configured to receive selection signal and at least two branch signals, and is configured to select, based on the selection signal, one of the branch signals and transmit a selected branch signal to the parallel branch; the serial wire, configured to organize signals output by the parallel branches into a serial signal; and a drive unit, connected to the serial wire for enhancing drive capability of the serial wire, where an output end of the drive unit is configured to output the serial signal.

公开(公告)号：US11687402B2

公开(公告)日：2023-06-27

申请号：US17467547

申请日：2021-09-07

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kangling Ji ,  Hongwen Li

IPC: G11C29/00 ,  G06F11/10 ,  G06F13/16 ,  H04B1/04

CPC classification number: G06F11/1004 ,  G06F11/1068 ,  G06F13/1668 ,  H04B1/04

Abstract: Provided are a data transmission circuit and a memory. The data transmission circuit includes: a normal reading module, which is connected to a normal storage array and configured to read and output data from the normal storage array; a redundant reading module, which is connected to a redundant storage array, and configured to read and output data from the redundant storage array; and an error detection operation module, which is connected to the normal reading module and the redundant reading module respectively, and configured to synchronously receive the read data output from the normal reading module and the redundant reading module, and perform error detection operation on the read data.

公开(公告)号：US11676642B2

公开(公告)日：2023-06-13

申请号：US17405107

申请日：2021-08-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Weibing Shang ,  Fengqin Zhang ,  Kangling Ji ,  Kai Tian ,  Xianjun Wu

IPC: G11C5/06 ,  G11C5/14 ,  G11C5/02 ,  H01L23/528

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C5/14 ,  H01L23/5286

Abstract: A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.

公开(公告)号：US11451219B2

公开(公告)日：2022-09-20

申请号：US17405110

申请日：2021-08-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Weibing Shang ,  Anping Qiu ,  Chan Chen ,  Kangling Ji

IPC: H03K5/134 ,  H03K5/00

Abstract: A delay circuit and a delay structure are provided. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal.

公开(公告)号：US12224039B2

公开(公告)日：2025-02-11

申请号：US18163323

申请日：2023-02-02

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kangling Ji

IPC: G11C8/18 ,  G11C8/10 ,  G11C8/12

Abstract: An address signal transmission circuit includes a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, where the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal; and a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, where the selection circuit inverts the second address signal to obtain the address inverted signal.

公开(公告)号：US12199645B2

公开(公告)日：2025-01-14

申请号：US17849942

申请日：2022-06-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Keqin Huang ,  Kangling Ji

IPC: H03M9/00 ,  G11C11/4093

Abstract: A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where first input end is configured to receive high level signal, second input end is configured to receive low level signal, control ends are connected to selection unit and output end is connected to serial wire, and selection unit is configured to receive selection signal and at least two branch signals and configured to select, based on selection signal, one branch signal and transmit it to parallel branch; serial wire configured to organize signals output by parallel branches into serial signal; and drive units connected in parallel with each other and connected to serial wire for enhancing drive capability of serial wire, output ends of drive units being connected with each other and configured to output serial signal, and each drive unit being disposed adjacent to a respective parallel branch.

公开(公告)号：US11861232B2

公开(公告)日：2024-01-02

申请号：US17657812

申请日：2022-04-04

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kangling Ji

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0673

Abstract: Embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data writing method thereof. The storage system is configured to: enter a write data copy mode in response to a write-copy enable signal; if at least two groups of data in multiple groups of data exported from multiple data ports are a same in the write data copy mode, define the at least two groups of data as a category; generate an identification signal that is used to indicate a data copy; transmit one group of data in the category to an interface of a memory array; and disconnect a transmission path between a data port corresponding to another group of data in the category and another interface of the memory array, wherein the memory array, in response to the write-copy enable signal and the identification signal.

公开(公告)号：US11693786B2

公开(公告)日：2023-07-04

申请号：US17171214

申请日：2021-02-09

Applicant: Changxin Memory Technologies, Inc.

Inventor： Kangling Ji ,  Weibing Shang

IPC: G11C8/12 ,  G06F12/10 ,  G06F7/58 ,  G06F12/14 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/408

CPC classification number: G06F12/10 ,  G06F7/582 ,  G06F12/1408 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  G06F2212/657

Abstract: A semiconductor memory is provided. The memory includes: a memory array; a row address processing unit configured to output a row address; a bank address processing unit configured to output a bank address; a column address processing unit configured to output a column address; and a mapping factor generating unit, configured to generate a mapping factor, wherein an output of the mapping factor generating unit is coupled to at least one of an output of the row address processing unit, an output of the bank address processing unit, and an output of the column address processing unit, and the output of the mapping factor generating unit is further coupled to the memory array, and wherein the memory array receives a result from logical processing performed on the mapping factor and at least one of the row address, the bank address, and the column address. The technical solutions of the embodiments of the present invention can improve the security, service life and reliability of the semiconductor memory.

公开(公告)号：US12106821B2

公开(公告)日：2024-10-01

申请号：US17439742

申请日：2021-07-08

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Enpeng Gao ,  Kangling Ji ,  Zengquan Wu

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/1066 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

Abstract: This application relates to a data transmission circuit, a method making it, and a storage device. The circuit includes a mode register data storage unit and an array area data storage unit. The mode register data storage unit outputs mode register data in response to a first clock signal; the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node, the array area data storage unit receives array area data in response to the first pointer signal, and outputs the array area data in response to the second pointer signal. This technic can accurately control the mode register data and the array area data to output through the respective output channels in turn.

公开(公告)号：US11971780B2

公开(公告)日：2024-04-30

申请号：US17810025

申请日：2022-06-30

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kangling Ji

IPC: G06F11/07 ,  G06F11/10 ,  G06F13/40

CPC classification number: G06F11/0793 ,  G06F11/0745 ,  G06F11/1048 ,  G06F13/4004

Abstract: A data error correction circuit and a data transmission circuit are disclosed. The data error correction circuit includes: a decoding circuit having an input terminal connected to a data bus, and configured to receive first data and a check code of the first data and output an error correction code of the first data based on the check code; and an error correction latch module having a first input terminal connected to the data bus and a second input terminal connected to an output terminal of the decoding circuit, and configured to latch the first data corresponding to the error correction code and generate and output second data according to the error correction code and the corresponding first data.