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    BRANCH PRUNING IN ARCHITECTURES WITH SPECULATION SUPPORT
    1.
    发明申请
    BRANCH PRUNING IN ARCHITECTURES WITH SPECULATION SUPPORT 有权
    在分支支持的分支机构中进行分配

    公开(公告)号：US20080244223A1

    公开(公告)日：2008-10-02

    申请号：US11695006

    申请日：2007-03-31

    申请人： Carlos Garcia Quinones ,  Jesus Sanchez ,  Carlos Madriles ,  Pedro Marcuello ,  Antonio Gonzalez

    发明人： Carlos Garcia Quinones ,  Jesus Sanchez ,  Carlos Madriles ,  Pedro Marcuello ,  Antonio Gonzalez

    IPC分类号： G06F15/00

    CPC分类号： G06F8/4441

    摘要： According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions executed will be smaller. However, since the applied optimization is speculative, the optimized version can be incorrect and some mechanism to recover from that situation is required. Thus, the quality of the produced code will be measured by taking into account both the final length of the code as well as the frequency of misspeculation.

    摘要翻译： 根据本发明主题的一个示例性实施例，本文描述的方法和装置用于生成静态代码片段的优化的推测版本。 在部分代码被优化的意义上，执行的指令数量将会更小。 然而，由于应用的优化是推测性的，因此优化版本可能是不正确的，并且需要从那种情况恢复的一些机制。 因此，所产生的代码的质量将通过考虑代码的最终长度以及错误的频率来测量。

    Selection of spawning pairs for a speculative multithreaded processor
    3.
    发明授权
    Selection of spawning pairs for a speculative multithreaded processor 有权
    为推测多线程处理器选择产卵对

    公开(公告)号：US07458065B2

    公开(公告)日：2008-11-25

    申请号：US10947034

    申请日：2004-09-21

    申请人： Jesus Sanchez ,  Carlos Garcia ,  Carlos Madriles ,  Peter Rundberg ,  Pedro Marcuello ,  Antonio Gonzalez

    发明人： Jesus Sanchez ,  Carlos Garcia ,  Carlos Madriles ,  Peter Rundberg ,  Pedro Marcuello ,  Antonio Gonzalez

    IPC分类号： G06F9/44 ,  G06F9/45

    CPC分类号： G06F9/4843

    摘要： A method for analyzing a set of spawning pairs, where each spawning pair identifies at least one speculative thread. The analysis may be practiced via software in a compiler, binary optimizer, standalone modeler, or the like. The analysis may include determining a predicted execution time for a sequence of program instructions, given the set of spawning pairs, for a target processor having a known number of thread units, where the target processor supports speculative multithreading. The method is further to select a spawning pair, according to a greedy approach, if the spawning pair provides a performance enhancement, in terms of decreased execution time due to increased parallelism, when the speculative thread is spawned during execution of a code sequence. Other embodiments are also described and claimed.

    摘要翻译： 一种用于分析一组产卵对的方法，其中每个产卵对标识至少一个推测性线程。 分析可以通过编译器中的软件，二进制优化器，独立建模器等来实现。 该分析可以包括：对于具有已知数量的线程单元的目标处理器，给定给定一组生成对的程序指令序列的预测执行时间，其中目标处理器支持推测性多线程。 如果在执行代码序列期间产生推测性线程时，根据贪婪方法，如果产卵对提供了性能增强，则由于增加的并行性而减少了执行时间，该方法进一步选择产卵对。 还描述和要求保护其他实施例。

    Multi-version register file for multithreading processors with live-in precomputation
    5.
    发明授权
    Multi-version register file for multithreading processors with live-in precomputation 有权
    用于具有实时预先计算的多线程处理器的多版本注册文件

    公开(公告)号：US08166282B2

    公开(公告)日：2012-04-24

    申请号：US10896585

    申请日：2004-07-21

    申请人： Carlos Madriles ,  Peter Rundberg ,  Jesus Sanchez ,  Carlos Garcia ,  Pedro Marcuello ,  Antonio Gonzalez

    发明人： Carlos Madriles ,  Peter Rundberg ,  Jesus Sanchez ,  Carlos Garcia ,  Pedro Marcuello ,  Antonio Gonzalez

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3842

    摘要： Disclosed are selected embodiments of a processor that may include a plurality of thread units and a register file architecture to support speculative multithreading. For at least one embodiment, live-in values for a speculative thread are computed via execution of a precomputation slice and are stored in a validation buffer for later validation. A global register file holds the committed architecture state generated by a non-speculative thread. Each thread unit includes a local register file. A directory indicates, for each architectural register, which speculative thread(s) have generated a value for the architectural register. Other embodiments are also described and claimed.

    摘要翻译： 公开了可以包括多个线程单元和用于支持推测性多线程的寄存器文件架构的处理器的选定实施例。 对于至少一个实施例，通过预计算片段的执行来计算推测线程的实时值，并将其存储在验证缓冲器中用于稍后的验证。 全局寄存器文件保存由非推测线程生成的承诺体系结构状态。 每个线程单元包括本地寄存器文件。 一个目录指示对于每个体系结构寄存器，哪些推测线程已经为架构寄存器生成了一个值。 还描述和要求保护其他实施例。

    Analyzer for spawning pairs in speculative multithreaded processor
    6.
    发明申请
    Analyzer for spawning pairs in speculative multithreaded processor 审中-公开
    用于推测多线程处理器中的产卵对的分析器

    公开(公告)号：US20060047495A1

    公开(公告)日：2006-03-02

    申请号：US10933076

    申请日：2004-09-01

    申请人： Jesus Sanchez ,  Carlos Garcia ,  Carlos Madriles ,  Peter Rundberg ,  Pedro Marcuello ,  Antonio Gonzalez

    发明人： Jesus Sanchez ,  Carlos Garcia ,  Carlos Madriles ,  Peter Rundberg ,  Pedro Marcuello ,  Antonio Gonzalez

    IPC分类号： G06F9/45

    CPC分类号： G06F9/4843

    摘要： A method for analyzing a set of spawning pairs, where each spawning pair identifies at least one speculative thread. The method, which may be practiced via software in a compiler or standalone modeler, determines execution time for a sequence of program instructions, given the set of spawning pairs, for a target processor having a known number of thread units, where the target processor supports speculative multithreading. Other embodiments are also described and claimed.

    摘要翻译： 一种用于分析一组产卵对的方法，其中每个产卵对标识至少一个推测性线程。 可以通过编译器或独立建模器中的软件来实现的方法，对于具有已知数量的线程单元的目标处理器，给定给定一组产卵对的一系列程序指令的执行时间，其中目标处理器支持 投机多线程。 还描述和要求保护其他实施例。

    Branch pruning in architectures with speculation support
    7.
    发明授权
    Branch pruning in architectures with speculation support 有权
    在建筑支持下进行分支修剪

    公开(公告)号：US08813057B2

    公开(公告)日：2014-08-19

    申请号：US11695006

    申请日：2007-03-31

    申请人： Carlos García Quiñones ,  Jesus Sanchez ,  Carlos Madriles ,  Pedro Marcuello ,  Antonio Gonzalez

    发明人： Carlos García Quiñones ,  Jesus Sanchez ,  Carlos Madriles ,  Pedro Marcuello ,  Antonio Gonzalez

    IPC分类号： G06F9/45

    CPC分类号： G06F8/4441

    摘要： According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions executed will be smaller. However, since the applied optimization is speculative, the optimized version can be incorrect and some mechanism to recover from that situation is required. Thus, the quality of the produced code will be measured by taking into account both the final length of the code as well as the frequency of misspeculation.

    摘要翻译： 根据本发明主题的一个示例性实施例，本文描述的方法和装置用于生成静态代码片段的优化的推测版本。 在部分代码被优化的意义上，执行的指令数量将会更小。 然而，由于应用的优化是推测性的，因此优化版本可能是不正确的，并且需要从那种情况恢复的一些机制。 因此，所产生的代码的质量将通过考虑代码的最终长度以及错误的频率来测量。

    Multi-version register file for multithreading processors with live-in precomputation
    8.
    发明申请
    Multi-version register file for multithreading processors with live-in precomputation 有权
    用于具有实时预先计算的多线程处理器的多版本注册文件

    公开(公告)号：US20060020775A1

    公开(公告)日：2006-01-26

    申请号：US10896585

    申请日：2004-07-21

    申请人： Carlos Madriles ,  Peter Rundberg ,  Jesus Sanchez ,  Carlos Garcia ,  Pedro Marcuello ,  Antonio Gonzalez

    发明人： Carlos Madriles ,  Peter Rundberg ,  Jesus Sanchez ,  Carlos Garcia ,  Pedro Marcuello ,  Antonio Gonzalez

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3842

    摘要： Disclosed are selected embodiments of a processor that may include a plurality of thread units and a register file architecture to support speculative multithreading. For at least one embodiment, live-in values for a speculative thread are computed via execution of a precomputation slice and are stored in a validation buffer for later validation. A global register file holds the committed architecture state generated by a non-speculative thread. Each thread unit includes a local register file. A directory indicates, for each architectural register, which speculative thread(s) have generated a value for the architectural register. Other embodiments are also described and claimed.

    摘要翻译： 公开了可以包括多个线程单元和用于支持推测性多线程的寄存器文件架构的处理器的选定实施例。 对于至少一个实施例，通过预计算片段的执行来计算推测线程的实时值，并将其存储在验证缓冲器中用于稍后的验证。 全局寄存器文件保存由非推测线程生成的承诺体系结构状态。 每个线程单元包括本地寄存器文件。 一个目录指示对于每个体系结构寄存器，哪些推测线程已经为架构寄存器生成了一个值。 还描述和要求保护其他实施例。

    Selection of spawning pairs for a speculative multithreaded processor
    9.
    发明申请
    Selection of spawning pairs for a speculative multithreaded processor 有权
    为推测多线程处理器选择产卵对

    公开(公告)号：US20060064692A1

    公开(公告)日：2006-03-23

    申请号：US10947034

    申请日：2004-09-21

    申请人： Jesus Sanchez ,  Carlos Garcia ,  Carlos Madriles ,  Peter Rundberg ,  Pedro Marcuello ,  Antonio Gonzalez

    发明人： Jesus Sanchez ,  Carlos Garcia ,  Carlos Madriles ,  Peter Rundberg ,  Pedro Marcuello ,  Antonio Gonzalez

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4843

    摘要： A method for analyzing a set of spawning pairs, where each spawning pair identifies at least one speculative thread. The analysis may be practiced via software in a compiler, binary optimizer, standalone modeler, or the like. The analysis may include determining a predicted execution time for a sequence of program instructions, given the set of spawning pairs, for a target processor having a known number of thread units, where the target processor supports speculative multithreading. The method is further to select a spawning pair, according to a greedy approach, if the spawning pair provides a performance enhancement, in terms of decreased execution time due to increased parallelism, when the speculative thread is spawned during execution of a code sequence. Other embodiments are also described and claimed.

    摘要翻译： 一种用于分析一组产卵对的方法，其中每个产卵对标识至少一个推测性线程。 分析可以通过编译器中的软件，二进制优化器，独立建模器等来实现。 该分析可以包括：对于具有已知数量的线程单元的目标处理器，给定给定一组生成对的程序指令序列的预测执行时间，其中目标处理器支持推测性多线程。 如果在执行代码序列期间产生推测性线程时，根据贪婪方法，如果产卵对提供了性能增强，则由于增加的并行性而减少了执行时间，该方法进一步选择产卵对。 还描述和要求保护其他实施例。