公开(公告)号：US20070020565A1

公开(公告)日：2007-01-25

申请号：US11429071

申请日：2006-05-08

申请人： Cha-Won Koh ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Kyeong-Koo Chi ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Seung-Pil Chung ,  Heung-Sik Park

发明人： Cha-Won Koh ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Kyeong-Koo Chi ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Seung-Pil Chung ,  Heung-Sik Park

IPC分类号： G03F7/26

CPC分类号： G03F7/0035 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.

摘要翻译： 提供制造半导体器件的方法。 还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。 可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。 可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。 在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。 可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。 可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。 可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。 蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

公开(公告)号：US07540970B2

公开(公告)日：2009-06-02

申请号：US11429071

申请日：2006-05-08

申请人： Cha-Won Koh ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Kyeong-Koo Chi ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Seung-Pil Chung ,  Heung-Sik Park

发明人： Cha-Won Koh ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Kyeong-Koo Chi ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Seung-Pil Chung ,  Heung-Sik Park

IPC分类号： C03C15/00

CPC分类号： G03F7/0035 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.

摘要翻译： 提供制造半导体器件的方法。 还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。 可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。 可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。 在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。 可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。 可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。 可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。 蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

公开(公告)号：US07491344B2

公开(公告)日：2009-02-17

申请号：US10703947

申请日：2003-11-04

申请人： Heung-Sik Park ,  Chang-Jin Kang ,  Tae-Hyuk Ahn ,  Kyeong-Koo Chi ,  Sang-Hun Seo

发明人： Heung-Sik Park ,  Chang-Jin Kang ,  Tae-Hyuk Ahn ,  Kyeong-Koo Chi ,  Sang-Hun Seo

IPC分类号： C23F1/00

CPC分类号： H01J37/32055 ,  H01L21/3065 ,  H01L21/78 ,  H05H1/44

摘要： Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.

摘要翻译： 本文公开了一种用于蚀刻物体的表面的方法，更具体地，蚀刻硅衬底的背面的方法。 具有硅面的物体被定位成与等离子体产生构件间隔预定间隔距离。 等离子体产生部件产生电弧等离子体以形成等离子体区域。 允许反应气体通过等离子体区域以产生具有高能量和高密度的自由基。 自由基与物体反应以蚀刻物体的表面。 物体的表面可以快速均匀地蚀刻。

公开(公告)号：US20060024932A1

公开(公告)日：2006-02-02

申请号：US11191488

申请日：2005-07-28

申请人： Heung-Sik Park ,  Kyeong-Koo Chi ,  Chang-Jin Kang

发明人： Heung-Sik Park ,  Kyeong-Koo Chi ,  Chang-Jin Kang

IPC分类号： H01L21/425

CPC分类号： H01L21/823842

摘要： Embodiments of the present invention provide methods of forming a semiconductor device including forming a polysilicon layer on a semiconductor substrate and doping the polysilicon layer with P-type impurities. The semiconductor substrate including the polysilicon layer is annealed and then an upper portion having a first thickness of the annealed polysilicon layer doped with the P-type impurities is removed. The first thickness is selected to remove defects formed in the polysilicon layer during doping and/or annealing thereof.

摘要翻译： 本发明的实施例提供了形成半导体器件的方法，该半导体器件包括在半导体衬底上形成多晶硅层，并用P型杂质掺杂多晶硅层。 包括多晶硅层的半导体衬底被退火，然后去除掺杂有P型杂质的退火多晶硅层的第一厚度的上部。 选择第一厚度以去除在其掺杂和/或退火期间在多晶硅层中形成的缺陷。

公开(公告)号：US07510934B2

公开(公告)日：2009-03-31

申请号：US11807544

申请日：2007-05-29

申请人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。 沟槽形成在衬底中，其间限定有效区域。 器件隔离膜位于衬底中的沟槽中。 隧道绝缘膜位于衬底的有源区上。 多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。 栅极间电介质膜延伸穿过浮栅和器件隔离膜。 控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。 沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。 器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。

公开(公告)号：US07242054B2

公开(公告)日：2007-07-10

申请号：US11190314

申请日：2005-07-26

申请人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L29/788 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。 沟槽形成在衬底中，其间限定有效区域。 器件隔离膜位于衬底中的沟槽中。 隧道绝缘膜位于衬底的有源区上。 多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。 栅极间电介质膜延伸穿过浮栅和器件隔离膜。 控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。 沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。 器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。

公开(公告)号：US20070231989A1

公开(公告)日：2007-10-04

申请号：US11807544

申请日：2007-05-29

申请人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L21/8238

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。 沟槽形成在衬底中，其间限定有效区域。 器件隔离膜位于衬底中的沟槽中。 隧道绝缘膜位于衬底的有源区上。 多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。 栅极间电介质膜延伸穿过浮栅和器件隔离膜。 控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。 沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。 器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。

公开(公告)号：US06562651B2

公开(公告)日：2003-05-13

申请号：US09916319

申请日：2001-07-30

申请人： Seung-pil Chung ,  Kyeong-Koo Chi ,  Jung-Sik Jeon

发明人： Seung-pil Chung ,  Kyeong-Koo Chi ,  Jung-Sik Jeon

IPC分类号： H01L2100

CPC分类号： H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes forming an insulated wiring pattern on a semiconductor substrate, and forming a lower interlayer insulating layer on the wiring pattern. A hard mask is formed on the lower insulating layer. Self-aligned contact holes are formed to expose the substrate under openings or gaps of the wiring pattern by partially etching the lower interlayer insulating layer be using the hard mask as an etch mask. A surface treatment process is carried out against surface of the substrate exposed through the self-aligned contact holes. Then, a first conductive layer is conformably formed over the whole surface of the substrate over which the surface treatment process is finished. At this time, projections are formed on sidewalls of the self-aligned contact holes. The first conductive layer is anisotropically etched to remove the projection. A second conductive layer fills completely the self-aligned contact holes.

公开(公告)号：US06534921B1

公开(公告)日：2003-03-18

申请号：US09708737

申请日：2000-11-09

申请人： Sang-Hun Seo ,  Kyeong-Koo Chi ,  Ji-Soo Kim ,  Chang-Woong Chu ,  Seung-Pil Chung

发明人： Sang-Hun Seo ,  Kyeong-Koo Chi ,  Ji-Soo Kim ,  Chang-Woong Chu ,  Seung-Pil Chung

IPC分类号： H01J724

CPC分类号： H01L21/31138 ,  B08B7/0035 ,  G03F7/427 ,  H05H1/44

摘要： A method of removing metal-containing polymeric material and ion implanted or plasma damaged photoresist from a surface using a plasma jet system, by generating radicals having high energy and high density from atmospheric plasma by introducing a reactant gas to the plasma, and placing the surface at a distance from the plasma, whereby ionic reaction on the surface is minimized while the removing action of the radicals on the surface is maintained.

摘要翻译： 通过使用等离子体喷射系统从表面去除含金属的聚合物材料和离子注入或等离子体损伤的光致抗蚀剂的方法，通过向等离子体引入反应气体，通过从等离子体引入具有高能量和高密度的自由基，并将表面 距离等离子体一定距离，由此表面上的离子反应被最小化，同时维持表面上的自由基的去除作用。

公开(公告)号：US07384843B2

公开(公告)日：2008-06-10

申请号：US11260377

申请日：2005-10-28

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/11521

摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.

摘要翻译： 制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。 使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。 凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。 控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。