公开(公告)号：US20070020565A1

公开(公告)日：2007-01-25

申请号：US11429071

申请日：2006-05-08

申请人： Cha-Won Koh ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Kyeong-Koo Chi ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Seung-Pil Chung ,  Heung-Sik Park

发明人： Cha-Won Koh ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Kyeong-Koo Chi ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Seung-Pil Chung ,  Heung-Sik Park

IPC分类号： G03F7/26

CPC分类号： G03F7/0035 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.

摘要翻译： 提供制造半导体器件的方法。 还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。 可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。 可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。 在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。 可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。 可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。 可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。 蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

公开(公告)号：US07540970B2

公开(公告)日：2009-06-02

申请号：US11429071

申请日：2006-05-08

申请人： Cha-Won Koh ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Kyeong-Koo Chi ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Seung-Pil Chung ,  Heung-Sik Park

发明人： Cha-Won Koh ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Kyeong-Koo Chi ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Seung-Pil Chung ,  Heung-Sik Park

IPC分类号： C03C15/00

CPC分类号： G03F7/0035 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.

摘要翻译： 提供制造半导体器件的方法。 还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。 可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。 可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。 在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。 可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。 可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。 可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。 蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

公开(公告)号：US20070077524A1

公开(公告)日：2007-04-05

申请号：US11529310

申请日：2006-09-29

申请人： Cha-Won Koh ,  Yool Kang ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Ji-Young Lee

发明人： Cha-Won Koh ,  Yool Kang ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Ji-Young Lee

IPC分类号： G03F7/26

CPC分类号： G03F7/40 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

摘要： Provided is a method for forming patterns of a semiconductor device. According to the method, first mask patterns may be formed on a substrate, and second mask patterns may be formed on sidewalls of each first mask pattern. Third mask patterns may fill spaces formed between adjacent second mask patterns, and the second mask patterns may be removed. A portion of the substrate may then be removed using the first and third mask patterns as etch masks.

摘要翻译： 提供了一种用于形成半导体器件的图案的方法。 根据该方法，可以在衬底上形成第一掩模图案，并且可以在每个第一掩模图案的侧壁上形成第二掩模图案。 第三掩模图案可以填充在相邻的第二掩模图案之间形成的空间，并且可以去除第二掩模图案。 然后可以使用第一和第三掩模图案作为蚀刻掩模去除衬底的一部分。

公开(公告)号：US20060131576A1

公开(公告)日：2006-06-22

申请号：US11296921

申请日：2005-12-08

申请人： Cha-Won Koh ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Hyun-Jae Kang ,  Jang-Ho Shin

发明人： Cha-Won Koh ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Hyun-Jae Kang ,  Jang-Ho Shin

IPC分类号： H01L23/58

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.

公开(公告)号：US07862988B2

公开(公告)日：2011-01-04

申请号：US11529310

申请日：2006-09-29

申请人： Cha-Won Koh ,  Yool Kang ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Ji-Young Lee

发明人： Cha-Won Koh ,  Yool Kang ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Ji-Young Lee

IPC分类号： G03F7/26

CPC分类号： G03F7/40 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

摘要： Provided is a method for forming patterns of a semiconductor device. According to the method, first mask patterns may be formed on a substrate, and second mask patterns may be formed on sidewalls of each first mask pattern. Third mask patterns may fill spaces formed between adjacent second mask patterns, and the second mask patterns may be removed. A portion of the substrate may then be removed using the first and third mask patterns as etch masks.

摘要翻译： 提供了一种用于形成半导体器件的图案的方法。 根据该方法，可以在衬底上形成第一掩模图案，并且可以在每个第一掩模图案的侧壁上形成第二掩模图案。 第三掩模图案可以填充在相邻的第二掩模图案之间形成的空间，并且可以去除第二掩模图案。 然后可以使用第一和第三掩模图案作为蚀刻掩模去除衬底的一部分。

公开(公告)号：US07582899B2

公开(公告)日：2009-09-01

申请号：US11296921

申请日：2005-12-08

申请人： Cha-Won Koh ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Hyun-Jae Kang ,  Jang-Ho Shin

发明人： Cha-Won Koh ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Hyun-Jae Kang ,  Jang-Ho Shin

IPC分类号： H01L23/58 ,  H01L29/10

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.

摘要翻译： 提供了具有覆盖测量标记的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底上的划线区域。 具有第一组线和空间图案的第一主刻度层和第二组线和空间图案组被布置在划线区域上。 线形的第二主刻度图案设置在第一组线和空间图案的空间区域上。 线状游标刻度图案设置在第二组线和空间图案的空间区域上。 在该方法中，在半导体衬底上形成具有第一组线和空间图案组以及第二组线和空间图案组的第一主刻度层。 线形的第二主刻度图案形成在第一组线和空间图案的空间区域上。 在第二组线和空间图案的空间区域上形成线形游标刻度图案。

公开(公告)号：US07678650B2

公开(公告)日：2010-03-16

申请号：US12453721

申请日：2009-05-20

申请人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

发明人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

IPC分类号： H01L21/8247

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521

摘要： Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

摘要翻译： 示例性实施例提供了一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。

公开(公告)号：US20090258473A1

公开(公告)日：2009-10-15

申请号：US12453721

申请日：2009-05-20

申请人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

发明人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

IPC分类号： H01L21/762

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521

摘要： Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

摘要翻译： 示例性实施例提供了一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。

公开(公告)号：US20070111441A1

公开(公告)日：2007-05-17

申请号：US11594808

申请日：2006-11-09

申请人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

发明人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521

摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。

公开(公告)号：US07560768B2

公开(公告)日：2009-07-14

申请号：US11594808

申请日：2006-11-09

申请人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

发明人： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521

摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。