摘要:
The present invention provides for reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating voltage coupled to the true node of the SRAM cell. If the floating voltage stays substantially constant, the value read from the SRAM cell is a high. If the floating voltage is drained to ground, the value read from the SRAM cell is a low.
摘要:
In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.
摘要:
A glitch protect valid cell and method for maintaining a desired logic state value in response to a glitch signal and a timing signal. The glitch protect valid cell may be integrated with a content addressable memory (CAM) array for indicating whether word data stored within the CAM is valid. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit each responsive to one another. The glitch protect circuit includes a propagation delay assembly and a restore assembly electrically coupled to one another. The propagation delay assembly includes a first pull down network and a NOR gate electrically coupled to one another. The restore assembly includes a second pull down network electrically coupled to the propagation delay assembly. The first pull down network is responsive to the glitch signal and the timing signal to selectively engage the NOR gate. In a glitch protect condition, the glitch protect valid cell restores the initial logic state value of the true valid bit despite at least one glitch signal invalidating the initial value. As such, the first pull down network resets the initial state value of the true valid bit according to the timing signal and the glitch signal supplied to the glitch protect circuit. The initial state value of a true valid bit is restored in the memory element with the second pull down network via the timing signal and a restore signal provided by an enabled pull up network within the NOR gate. Specifically, the second pull down network is responsive to the pull up network selectively enabled within the NOR gate and resets the complement valid bit in the memory element to consequently restore the initial state value of the true valid bit.
摘要:
An apparatus and methods for predicting and/or for calibrating memory yields due to process defects and/or device variations, including determining a model of a memory cell, identifying a subset of parameters associated with the model, determining and executing a refined model using the parameters, determining a predicted probability the simulated memory cell will be operational based on the simulated operation of the refined model, determining yield prediction information from the predicted probability, and determining the minimum number of repair elements to include in a memory array design to insure a desired yield percentage based on the yield prediction information.
摘要:
In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a first group of transistors adapted to store the bit and a second group of transistors adapted to affect a signal asserted during a read operation on a read bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the second group of transistors affects the signal asserted during the read operation on the read bit line coupled to the cell. Numerous other aspects are provided.
摘要:
A needle assembly with needle shield that is connected to the needle hub by a tether. The tether prevents unwanted proximal movement of the needle with respect to the needle shield once the needle has been withdrawn into the needle shield. The tether is maintained in its compressed state by use of the invention for ease of assembly.
摘要:
A medical needle assembly includes a needle cannula having a body and a tip. The tip is disposed at a distal end of the cannula. An elongate member has a first end and a second end. The first end is fixedly attached to the body of the needle cannula at a connection point and the second end extends radially outward from the needle body. A shield is slidingly mounted to the needle for movement between a proximal position to a distal position. The shield includes a shield body having a central chamber, a distal end and a proximal end as well as a plate secured to the shield body and defining an aperture. As the shield is moved from the proximal position to the distal position, the place displaces the second end of the elongate member to a position near the needle cannula, permitting the elongate member to pass through the aperture. When the shield is in the distal position, the send end of the elongate member extends radially outward from the needle body, preventing passage of the elongate member through the aperture. The elongate member may be a leaf spring. A feature may be secured to the body of the cannula to restrict movement of the shield with respect to the needle.
摘要:
A disk is manufactured having a reduced capacity based on a quantity of addressable and non-addressable portions. The method of formatting the disk comprises identifying a first quantity of the storage portions; and labeling the first quantity of storage portions as non-addressable storage portions such that the non-addressable storage portions cannot be accessed by a user or a disk drive. The first quantity of storage portions may include addressable portions designated as non-addressable portions.
摘要:
Data on a master is read into a master image file, and the master image file is manipulated to include a benchmark comprising tracking and verification information tied to at least a portion of the master image file. Thus, a copied-to storage media as copied from the master image file also includes such benchmark, a data alteration of the master image file causes a mis-match with regard to the benchmark in such master image file, and a data alteration of the copied-to storage media also causes a mis-match with regard to the benchmark in such storage media as copied from such master image file. The benchmark may include a part identifier and a security identifier.
摘要:
A k-to-2k decoder is provided. Within the final stage of a k-to-2k decoder is a plurality of word line drivers. These word line drivers utilize clocking signals to fire word lines to a memory array. However, power consumption by clocks has become a serious issue with the increase component density on silicon wafers. To alleviate the problem, signals from the first stage of the k-to-2k decoder provide enablement signals to Local Clock Buffers (LCBs) that allow the word line drivers to fire. The enablement signal reduces the number of active buffers and signals carried to word line drivers, reducing power consumption.