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公开(公告)号：US07289370B2
公开(公告)日：2007-10-30
申请号：US11186606
申请日：2005-07-21
IPC分类号： G11C16/04
CPC分类号： G11C11/413 , G11C7/06 , G11C7/1006 , G11C7/12
摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.
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2.发明申请公开(公告)号：US20080117695A1
公开(公告)日：2008-05-22
申请号：US11560428
申请日：2006-11-16
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译： 存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。 字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_wl和write_wl信号由字线解码器基于在下一周期中是执行读操作还是写操作生成。 字线解码器包括具有用于接收write_wl信号的输入的缓冲器和用于输出write_wl信号的延迟版本的输出。 基于read_wl信号和延迟的write_wl信号，字线信号由字线解码器激活。 这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。
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3.发明申请Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays 审中-公开Domino SRAM数组中不平衡读/写路径的延迟机制公开(公告)号：US20080212396A1
公开(公告)日：2008-09-04
申请号：US12098715
申请日：2008-04-07
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_w1 and write_w1 signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_w1 signal and an output for outputting a delayed version of the write_w1 signal. The wordline signal is activated by the wordline decoder based on the read_w1 signal and the delayed write_w1 signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译： 存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。 字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_w 1和write_w 1信号由字线解码器基于在下一个周期是执行读操作还是写操作生成。 字线解码器包括具有用于接收write_w 1信号的输入的缓冲器和用于输出write_w 1信号的延迟版本的输出。 字线信号由字线解码器基于read_w 1信号和延迟的write_w 1信号激活。 这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。
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4.发明授权公开(公告)号：US07400550B2
公开(公告)日：2008-07-15
申请号：US11560428
申请日：2006-11-16
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译： 存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。 字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_wl和write_wl信号由字线解码器基于在下一周期中是执行读操作还是写操作生成。 字线解码器包括具有用于接收write_wl信号的输入的缓冲器和用于输出write_wl信号的延迟版本的输出。 基于read_wl信号和延迟的write_wl信号，字线信号由字线解码器激活。 这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。
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5.发明授权Lower power and reduced device split local and continuous bitline for domino read SRAMs 有权降低功耗和减少器件分割本地和连续位线用于多米诺式读取SRAM公开(公告)号：US06901003B2
公开(公告)日：2005-05-31
申请号：US10616847
申请日：2003-07-10
IPC分类号： G11C7/18 , G11C11/419 , G11C11/00
CPC分类号： G11C7/18 , G11C11/419
摘要： A method, an apparatus, and a computer program are provided to reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating voltage coupled to the true node of the SRAM cell. If the floating voltage stays substantially constant, the value read from the SRAM cell is a high. If the floating voltage is drained to ground, the value read from the SRAM cell is a low.
摘要翻译： 提供了一种方法，装置和计算机程序来从SRAM单元读取标记。 在写真线上生成一个低值。 在连续的位线上生成高值。 通过使用耦合到SRAM单元的真实节点的浮动电压来评估SRAM单元的真实节点。 如果浮置电压保持大致恒定，则从SRAM单元读取的值为高。 如果浮置电压耗尽地，则从SRAM单元读取的值为低电平。
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公开(公告)号：US06657886B1
公开(公告)日：2003-12-02
申请号：US10140549
申请日：2002-05-07
IPC分类号： G11C1140
CPC分类号： G11C11/419
摘要： A high performance domino static random access memory (SRAM) is provided. The domino SRAM includes a plurality of local cell groups. Each of the plurality of local cell groups includes a plurality of SRAM cells and a local true bitline coupled to each of the plurality of SRAM cells of each local cell group. A continuous complement bitline is coupled to each of the plurality of local cell groups and is coupled to each of the plurality of SRAM cells of each local cell group. For a write to the SRAM cell complement node, only driving the continuous complement bitline is required. The domino SRAM reduces the number of required wires and required transistors as compared to prior art domino SRAM and thus the area needed and power consumption are reduced for the domino SRAM.
摘要翻译： 提供了高性能的多米诺骨牌静态随机存取存储器（SRAM）。 多米诺SRAM包括多个本地小区组。 多个本地单元组中的每一个包括耦合到每个本地单元组的多个SRAM单元中的每一个的多个SRAM单元和本地真位线。 连续的补码位线耦合到多个局部单元组中的每一个，并耦合到每个本地单元组的多个SRAM单元中的每一个。 要写入SRAM单元补码节点，只需要驱动连续的补码位线。 与现有技术的多米诺骨牌SRAM相比，多米诺骨牌SRAM减少了所需的电线和所需的晶体管数量，因此为多米诺骨牌SRAM降低了所需的面积和功耗。
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7.发明申请Asymmetrical Random Access Memory Cell, A Memory Comprising Asymmetrical Memory Cells And A Method To Operate Such A Memory 有权非对称随机存取存储器单元，包含不对称存储单元的存储器和一种操作这样的存储器的方法公开(公告)号：US20070165447A1
公开(公告)日：2007-07-19
申请号：US11623443
申请日：2007-01-16
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl). Furthermore the invention relates to a random access memory comprising a plurality of such asymmetrical random access memory cells and to a method to operate such a random access memory.
摘要翻译： 非对称随机存取存储单元（1）包括交叉耦合的反相器（2,3），它们通过一对互补位线的分开的位线（blt，blc）在其节点（22,32）处被驱动，所述位线连接 通过通过晶体管（21,31），其中随机存取存储单元通过具有不对称物理行为的交叉耦合反相器（2,3）不对称，从而存在逆变器的不同切换阈值，并且通过 - 晶体管（21,31）由单独的受控字线（w1，wwl）驱动。 此外，本发明涉及包括多个这样的非对称随机存取存储器单元的随机存取存储器和一种操作这样的随机存取存储器的方法。
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8.发明授权Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells 有权不对称随机存取存储器单元，以及包含不对称存储单元的存储器公开(公告)号：US07535750B2
公开(公告)日：2009-05-19
申请号：US11623443
申请日：2007-01-16
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl).
摘要翻译： 包括交叉耦合的反相器（2,3）的不对称随机存取存储器单元（1），它们通过一对互补位线的分开的位线（blt，blc）在它们的节点（22,32）处被驱动， 通过通过晶体管（21,31），其中随机存取存储单元通过具有不对称物理行为的交叉耦合反相器（2,3）不对称，从而存在逆变器的不同切换阈值，并且通过 - 晶体管（21,31）由单独的受控字线（w1，wwl）驱动。
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公开(公告)号：US20060023552A1
公开(公告)日：2006-02-02
申请号：US10891770
申请日：2004-07-15
IPC分类号： G11C5/14
CPC分类号： G11C7/22
摘要： A method, an apparatus, and a computer program are provided for reducing power consumption and area of a memory subsystem. In many typical memory subsystems, dynamic topologies are employed to detect logic levels in memory; however, dynamic topologies often require clocking. Both power and area are consumed as a result of the clocking. To combat the consumption of power and area, the memory subsystem has been modified so that an enable signal, that must be present, is utilized instead to provide the clocking.
摘要翻译： 提供了一种方法，装置和计算机程序，用于降低存储子系统的功耗和面积。 在许多典型的存储器子系统中，采用动态拓扑来检测存储器中的逻辑电平; 然而，动态拓扑通常需要时钟。 功率和面积都是由于时钟而消耗的。 为了消除功率和面积的消耗，存储器子系统已经被修改，使得必须存在必须存在的使能信号来提供时钟。
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10.发明授权Compact SRAM cell layout for implementing one-port or two-port operation 失效紧凑的SRAM单元布局，用于实现单端口或双端口操作公开(公告)号：US06737685B2
公开(公告)日：2004-05-18
申请号：US10045755
申请日：2002-01-11
IPC分类号： H01L2710
CPC分类号： G11C11/412 , G11C8/16 , H01L27/1104 , Y10S257/903
摘要： Compact static random access memory (SRAM) cell layouts are provided for implementing one-port and two-port operation. The SRAM cell layouts include a plurality of field effect transistors (FETs). The plurality of FETs defines a storage cell and a pair of wordline FETs coupled to the storage cell. Each of the plurality of FETs has a device structure extending in a single direction. The device structure of each of the plurality of FETs includes a diffusion layer, a polysilicon layer and first metal layer. A local interconnect connects the diffusion layer, the polysilicon layer and the first metal layer. Each of the pair of wordline FETs having a gate input connected to a wordline. The wordline including a single wordline for implementing one-port operation or two separate wordline connections for implementing two-port operation. The local interconnect includes a metal local interconnect that lays on the diffusion and polysilicon layers for electrically connecting diffusion and polysilicon layers and a metal contact that extends between the metal local interconnect and the first level metal for electrically connecting diffusion and polysilicon layers and the first level metal. Alternatively, a metal contact lays directly on the diffusion and polysilicon layers electrically connecting diffusion and polysilicon layers and the first level metal. The local interconnect further includes a conduction layer disposed on a butted diffusion connection of diffusion-p type and diffusion-n type and a metal local interconnect disposed on the conduction layer.
摘要翻译： 提供紧凑型静态随机存取存储器（SRAM）单元布局，用于实现单端口和双端口操作。 SRAM单元布局包括多个场效应晶体管（FET）。 多个FET限定存储单元和耦合到存储单元的一对字线FET。 多个FET中的每一个具有沿单个方向延伸的器件结构。 多个FET中的每一个的器件结构包括扩散层，多晶硅层和第一金属层。 局部互连连接扩散层，多晶硅层和第一金属层。 一对字线FET中的每一个具有连接到字线的栅极输入。 字线包括用于实现单端口操作的单个字线或用于实现双端口操作的两个单独的字线连接。 局部互连包括位于扩散层和多晶硅层上用于电连接扩散和多晶硅层的金属局部互连和在金属局部互连和第一级金属之间延伸的金属接触件，用于电连接扩散层和多晶硅层以及第一级 金属。 或者，金属接触直接放置在电连接扩散和多晶硅层和第一级金属的扩散层和多晶硅层上。 局部互连还包括设置在扩散-P型和扩散型n的对接扩散连接上的导电层和设置在导电层上的金属局部互连。
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