公开(公告)号：US20060023552A1

公开(公告)日：2006-02-02

申请号：US10891770

申请日：2004-07-15

申请人： Anthony Gus Aipperspach ,  Peichun Peter Liu ,  Jieming Qi

发明人： Anthony Gus Aipperspach ,  Peichun Peter Liu ,  Jieming Qi

IPC分类号： G11C5/14

CPC分类号： G11C7/22

摘要： A method, an apparatus, and a computer program are provided for reducing power consumption and area of a memory subsystem. In many typical memory subsystems, dynamic topologies are employed to detect logic levels in memory; however, dynamic topologies often require clocking. Both power and area are consumed as a result of the clocking. To combat the consumption of power and area, the memory subsystem has been modified so that an enable signal, that must be present, is utilized instead to provide the clocking.

摘要翻译： 提供了一种方法，装置和计算机程序，用于降低存储子系统的功耗和面积。 在许多典型的存储器子系统中，采用动态拓扑来检测存储器中的逻辑电平; 然而，动态拓扑通常需要时钟。 功率和面积都是由于时钟而消耗的。 为了消除功率和面积的消耗，存储器子系统已经被修改，使得必须存在必须存在的使能信号来提供时钟。

公开(公告)号：US06737685B2

公开(公告)日：2004-05-18

申请号：US10045755

申请日：2002-01-11

申请人： Anthony Gus Aipperspach ,  Donald Wayne Plass

发明人： Anthony Gus Aipperspach ,  Donald Wayne Plass

IPC分类号： H01L2710

CPC分类号： G11C11/412 ,  G11C8/16 ,  H01L27/1104 ,  Y10S257/903

摘要： Compact static random access memory (SRAM) cell layouts are provided for implementing one-port and two-port operation. The SRAM cell layouts include a plurality of field effect transistors (FETs). The plurality of FETs defines a storage cell and a pair of wordline FETs coupled to the storage cell. Each of the plurality of FETs has a device structure extending in a single direction. The device structure of each of the plurality of FETs includes a diffusion layer, a polysilicon layer and first metal layer. A local interconnect connects the diffusion layer, the polysilicon layer and the first metal layer. Each of the pair of wordline FETs having a gate input connected to a wordline. The wordline including a single wordline for implementing one-port operation or two separate wordline connections for implementing two-port operation. The local interconnect includes a metal local interconnect that lays on the diffusion and polysilicon layers for electrically connecting diffusion and polysilicon layers and a metal contact that extends between the metal local interconnect and the first level metal for electrically connecting diffusion and polysilicon layers and the first level metal. Alternatively, a metal contact lays directly on the diffusion and polysilicon layers electrically connecting diffusion and polysilicon layers and the first level metal. The local interconnect further includes a conduction layer disposed on a butted diffusion connection of diffusion-p type and diffusion-n type and a metal local interconnect disposed on the conduction layer.

摘要翻译： 提供紧凑型静态随机存取存储器（SRAM）单元布局，用于实现单端口和双端口操作。 SRAM单元布局包括多个场效应晶体管（FET）。 多个FET限定存储单元和耦合到存储单元的一对字线FET。 多个FET中的每一个具有沿单个方向延伸的器件结构。 多个FET中的每一个的器件结构包括扩散层，多晶硅层和第一金属层。 局部互连连接扩散层，多晶硅层和第一金属层。 一对字线FET中的每一个具有连接到字线的栅极输入。 字线包括用于实现单端口操作的单个字线或用于实现双端口操作的两个单独的字线连接。 局部互连包括位于扩散层和多晶硅层上用于电连接扩散和多晶硅层的金属局部互连和在金属局部互连和第一级金属之间延伸的金属接触件，用于电连接扩散层和多晶硅层以及第一级 金属。 或者，金属接触直接放置在电连接扩散和多晶硅层和第一级金属的扩散层和多晶硅层上。 局部互连还包括设置在扩散-P型和扩散型n的对接扩散连接上的导电层和设置在导电层上的金属局部互连。

公开(公告)号：US06538522B1

公开(公告)日：2003-03-25

申请号：US09977423

申请日：2001-10-15

申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  David Michael Friend ,  Nghia Van Phan

发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  David Michael Friend ,  Nghia Van Phan

IPC分类号： H03B2700

CPC分类号： H03K3/0315

摘要： Measurement methods and a ring oscillator circuit are provided for evaluating dynamic circuits. The ring oscillator circuit includes a one-shot pulse generator receiving a single transition input signal and producing a pulse output signal having a rising transition and falling transition. The dynamic circuit to be evaluated is coupled to an output of the one-shot pulse generator receiving the pulse output signal of the one-shot pulse generator and producing a delayed output pulse at an output. A divide-by-two circuit is coupled to the output of the dynamic circuit to be evaluated. An output signal of the divide-by-two circuit is fed back to the one-shot pulse generator, and the cycle is repeated, thus oscillating. A multiplexer is connected between output of the dynamic circuit to be evaluated and the divide-by-two circuit. The multiplexer receives the pulse output of the one-shot pulse generator and includes a select input for selecting the output of the dynamic circuit to be evaluated or the pulse output of the one-shot pulse generator. By inserting the evaluation circuit into a path that can be multiplexed in and out of the oscillator path, and by measuring the difference between the frequency with and without the evaluation circuit in the path, the performance of the evaluation circuit can be accurately determined.

摘要翻译： 提供测量方法和环形振荡器电路用于评估动态电路。 环形振荡器电路包括接收单个转换输入信号的单触发脉冲发生器，并产生具有上升的转换和下降转换的脉冲输出信号。 要评估的动态电路耦合到接收单触发脉冲发生器的脉冲输出信号的单触发脉冲发生器的输出，并在输出端产生延迟的输出脉冲。 二分之一电路耦合到待评估的动态电路的输出。 二分之一电路的输出信号反馈给单触发脉冲发生器，重复循环，从而振荡。 多路复用器连接在待评估的动态电路的输出端与分频电路之间。 复用器接收单触发脉冲发生器的脉冲输出，并且包括用于选择要评估的动态电路的输出或单触发脉冲发生器的脉冲输出的选择输入。 通过将评估电路插入到可以复用在振荡器路径中的路径之外，并且通过测量路径中具有和不具有评估电路的频率之间的差异，可以准确地确定评估电路的性能。

公开(公告)号：US06247166B1

公开(公告)日：2001-06-12

申请号：US09104621

申请日：1998-06-25

申请人： Anthony Gus Aipperspach ,  Peter Thomas Freiburger

发明人： Anthony Gus Aipperspach ,  Peter Thomas Freiburger

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method, computer program product and apparatus for assembling array and datapath macros are provided for very large scale integrated (VLSI) semiconductor integrated circuits. User selections are received for a hierarchical macro to be created. The user selections include a command list of multiple leaf cell build commands. X and Y placer pointers are initialized. A next build command is obtained from the command list and a command type is identified. Responsive to identifying a next leaf cell build command in a leaf cell group, a user selected schematic or physical view is identified. A corresponding leaf cell view is read for the user selected schematic or physical view. X and Y sizes are obtained for the leaf cell view. Then the leaf cell is oriented and placed. Next X and Y placer pointers are calculated and the sequential steps are repeated until a last leaf cell build command in the leaf cell group is found. Then the sequential steps return to obtain a next build command from the command list. Connections to adjacent leaf cells are provided by abutting cells together. Port and pin connections from the periphery of the array of placed leaf cells are propagated to a next hierarchical level of the hierarchical macro being created.

摘要翻译： 为大规模集成（VLSI）半导体集成电路提供了一种用于组装阵列和数据路径宏的计算机程序产品和设备。 接收到要创建的分层宏的用户选择。 用户选择包括多个叶单元构建命令的命令列表。 X和Y指针被初始化。 从命令列表中获取下一个构建命令，并识别命令类型。 响应于在叶单元组中识别下一个叶细胞构建命令，识别用户选择的示意图或物理视图。 为用户选择的原理图或物理视图读取相应的叶单元格视图。 获得叶单元格视图的X和Y尺寸。 然后叶细胞被定向和放置。 计算下一个X和Y填充指针，并重复顺序步骤，直到找到叶细胞组中的最后一个叶细胞构建命令。 然后，顺序步骤返回以从命令列表中获取下一个构建命令。 通过邻接的细胞在一起提供与相邻叶细胞的连接。 从放置的叶单元阵列的外围的端口和引脚连接被传播到正在创建的分层宏的下一层级。

公开(公告)号：US06205063B1

公开(公告)日：2001-03-20

申请号：US09140031

申请日：1998-08-26

申请人： Anthony Gus Aipperspach ,  Sheldon Bernard Levenstein

发明人： Anthony Gus Aipperspach ,  Sheldon Bernard Levenstein

IPC分类号： G11C700

CPC分类号： G11C29/787 ,  G11C29/802 ,  G11C29/812

摘要： Defects in memory circuit (100) are efficiently corrected by selectively blowing fuses in a first plurality of fuses to describe a cell location of a defective cell within any of several memory array portions (110). Fuses in a second plurality of fuses are blown to describe indicate the particular memory array portion (112) containing the defective memory cell. During operation of the memory circuit (100), the cell location is forwarded to the memory array portion (112) containing the defective memory cell and a redundant memory cell (206) is used for data storage at the memory array portion (112) having a defective memory cell.

摘要翻译： 存储器电路（100）中的缺陷通过有选择地在第一多个保险丝中熔断以描述几个存储器阵列部分（110）中的任一个内的有缺陷的单元的单元位置而被有效地校正。 熔断第二多个保险丝中的保险丝被熔断以描述指示包含有缺陷存储器单元的特定存储器阵列部分（112）。 在存储器电路（100）的操作期间，单元位置被转发到包含有缺陷存储单元的存储器阵列部分（112），并且冗余存储单元（206）被用于在存储器阵列部分（112）处的数据存储， 有缺陷的存储单元。

公开(公告)号：US5835502A

公开(公告)日：1998-11-10

申请号：US673258

申请日：1996-06-28

申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Murali Vaddigiri ,  Paul Wong

发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Murali Vaddigiri ,  Paul Wong

IPC分类号： G06F12/16 ,  G06F11/22 ,  G11C29/02 ,  G11C29/12 ,  G11C29/32 ,  G06F11/00

CPC分类号： G11C29/32

摘要： A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.

摘要翻译： 一种用于处理阵列内置自检系统中的可变数据字宽度和阵列深度的方法和装置，用于使用单个控制器来测试多个存储器阵列。 每个阵列包括预定的行和列地址深度和数据字宽度。 每个阵列还包括扫描寄存器。 生成通用测试数据字并将其发送到每个阵列的扫描寄存器。 通用长度测试数据字的长度取决于最大行地址深度，最大列地址深度和/或最大数据字宽度。 超过特定阵列的列地址深度，行地址深度和/或数据字宽度的测试数据字的一部分从特定阵列的扫描寄存器的结尾偏移。

公开(公告)号：US5778243A

公开(公告)日：1998-07-07

申请号：US675315

申请日：1996-07-03

申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Binta Minesh Patel ,  Nghia Van Phan ,  Michael James Rohn ,  Salvatore Nicholas Storino ,  Bryan Joe Talik ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Binta Minesh Patel ,  Nghia Van Phan ,  Michael James Rohn ,  Salvatore Nicholas Storino ,  Bryan Joe Talik ,  Gregory John Uhlmann

IPC分类号： G06F12/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G11C8/16 ,  G06F12/02 ,  G06F9/40

CPC分类号： G06F9/30141 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3851 ,  G11C8/16

摘要： A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.

摘要翻译： 一种用于多线程计算机系统中的多线程存储器（和相关方法），其中多个线程与单个处理器一起使用。 多线程内存包括：多线程存储单元; 至少一个写入解码器，向所选择的多线程存储单元提供信息; 以及至少一个读取解码器从所选择的多线程存储单元访问信息。 每个多线程存储单元包括：N个存储元件，其中N≥2，N个存储元件中的每一个具有线程通信内容; 写入接口，向所述小区内存储元件提供信息; 以及从单元内存储元件读取信息的读取接口。 至少一个小区内读取和写入接口至少部分地通过识别对应的线程来选择线程对应内容之一，以实现小区内线程通信的内容选择。

公开(公告)号：US07729188B2

公开(公告)日：2010-06-01

申请号：US12029010

申请日：2008-02-11

申请人： Anthony Gus Aipperspach ,  Phil Christopher Felice Paone ,  Brian Joy Reed ,  David Edward Schmitt ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  Phil Christopher Felice Paone ,  Brian Joy Reed ,  David Edward Schmitt ,  Gregory John Uhlmann

IPC分类号： G11C7/00

CPC分类号： G11C17/18 ,  G11C7/062 ,  G11C7/065 ,  G11C17/16 ,  G11C29/026

摘要： A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.

摘要翻译： 一种用于实现eFuse读出放大器的方法和电路，以及设置有被摄体电路的设计结构。 感测电路包括一对交叉耦合的反相器，每个由一对串联的P沟道场效应晶体管（PFET）和N沟道场效应晶体管（NFET）形成。 第一上拉电阻耦合在正电压供电轨和感测电路的第一感测节点之间。 第二上拉电阻耦合在感测电路的正电压供电轨道和第二感测节点之间。 第一位线耦合到感测电路的第一感测节点，耦合到感测电路的第二感测节点的第二位线。 相应的参考电阻器和相应的eFuse单元之一选择性地耦合到第一位线和第二位线。

公开(公告)号：US07532057B2

公开(公告)日：2009-05-12

申请号：US11872873

申请日：2007-10-16

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil C. Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil C. Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

IPC分类号： H01H37/76 ,  H01H85/00

CPC分类号： G11C17/18 ,  G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure for electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal enables the first current source, the second current source and closes the first switch and the second switch, creating voltage drops across the electrically programmable fuse and the reference resistance. When the precharge signal goes inactive, the first current source and the second current source are shut off, and, at the same time the first switch and the second switch are opened. A latching circuit uses a difference in the voltage drops when the precharge signal goes inactive to store a state of the electrically programmable fuse, indicative of whether the electrically programmable fuse is blown or unblown.

摘要翻译： 一种用于电可编程熔丝检测电路的设计结构，其具有电可编程熔丝和参考电阻。 第一电流源通过第一开关耦合到电可编程保险丝。 第二电流源通过第二开关耦合到参考电阻。 预充电信号使得第一电流源，第二电流源能够闭合第一开关和第二开关，从而在电可编程保险丝和参考电阻之间产生电压降。 当预充电信号不起作用时，第一电流源和第二电流源被切断，同时第一开关和第二开关断开。 当预充电信号无效以存储电可编程熔丝的状态时，锁存电路使用电压降的差异，指示电可编程熔丝是否被吹制或未被吹出。

公开(公告)号：US07318209B2

公开(公告)日：2008-01-08

申请号：US10616881

申请日：2003-07-10

申请人： Anthony Gus Aipperspach ,  David William Boerstler ,  Dieter Wendel

发明人： Anthony Gus Aipperspach ,  David William Boerstler ,  Dieter Wendel

IPC分类号： G06F17/50

CPC分类号： H03K5/1565 ,  H03L7/06

摘要： A method and an apparatus are provided for limiting a pulse width in a chip clock design of a circuit. The circuit receives a clock signal having a clock pulse width. The clock pulse width of the clock signal is detected. It is determined whether the clock pulse width is larger than a maximum clock pulse width. Upon a determination that the clock pulse width is larger than a maximum clock pulse width, the clock pulse width of the clock signal is limited.

摘要翻译： 提供了一种用于限制电路的芯片时钟设计中的脉冲宽度的方法和装置。 该电路接收具有时钟脉冲宽度的时钟信号。 检测时钟信号的时钟脉冲宽度。 确定时钟脉冲宽度是否大于最大时钟脉冲宽度。 在确定时钟脉冲宽度大于最大时钟脉冲宽度的情况下，时钟信号的时钟脉冲宽度受到限制。