公开(公告)号：US06754120B1

公开(公告)日：2004-06-22

申请号：US10364178

申请日：2003-02-11

申请人： Chad Bellows ,  Wayne Richardson ,  Lawrence Lai ,  Kurt Knorpp

发明人： Chad Bellows ,  Wayne Richardson ,  Lawrence Lai ,  Kurt Knorpp

IPC分类号： G11C700

CPC分类号： G11C7/1051 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C11/4096

摘要： Described are memory systems designed to emphasize differences between memory-cell access times. As a consequence of these access-time variations, data read from different memory cells arrives at some modified output circuitry. The output circuitry sequentially offloads the data in the order of arrival. Data access times are reduced because the output circuitry can begin shifting the first data to arrive before the slower data is ready for capture. Differences between data access times for cells in a given memory array may be emphasized using differently sized sense amplifiers, routing, or both.

摘要翻译： 描述了旨在强调存储单元访问时间之间的差异的存储器系统。 作为这些访问时间变化的结果，从不同存储器单元读取的数据到达一些修改的输出电路。 输出电路按顺序卸载数据。 数据访问时间减少，因为输出电路可以在较慢的数据准备好捕捉之前开始移位第一个数据到达。 可以使用不同大小的读出放大器，路由或两者来强调给定存储器阵列中的单元的数据访问时间之间的差异。

公开(公告)号：US20070250677A1

公开(公告)日：2007-10-25

申请号：US11767863

申请日：2007-06-25

申请人： Frederick Ware ,  Craig Hampel ,  Wayne Richardson ,  Chad Bellows ,  Lawrence Lai

发明人： Frederick Ware ,  Craig Hampel ,  Wayne Richardson ,  Chad Bellows ,  Lawrence Lai

IPC分类号： G06F13/372

CPC分类号： G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

摘要： A multi-mode memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval is imposed between successive accesses to a given row of the storage cells. Data path circuitry is provided to transfer data between the plurality of storage banks and an external signal path during first and second modes of operation of the memory device. During the first mode of operation a first data item is transferred, in response to a first memory access request, during a first time interval that is not longer than the minimum time interval. During the second mode of operation a plurality of data items are transferred during the first time interval, in response to a plurality of memory access requests.

摘要翻译： 多模式存储器件。 提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为在对存储单元的给定行的连续访问之间至少施加最小访问时间间隔。 提供数据路径电路以在存储器件的第一和第二操作模式期间在多个存储体之间传送数据和外部信号路径。 在第一操作模式期间，响应于第一存储器访问请求，在不长于最小时间间隔的第一时间间隔期间传送第一数据项。 在第二操作模式期间，响应于多个存储器访问请求，在第一时间间隔期间传送多个数据项。

公开(公告)号：US20060039227A1

公开(公告)日：2006-02-23

申请号：US10920508

申请日：2004-08-17

申请人： Lawrence Lai ,  Wayne Richardson ,  Chad Bellows

发明人： Lawrence Lai ,  Wayne Richardson ,  Chad Bellows

IPC分类号： G11C7/10

CPC分类号： G11C7/1042 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2227

摘要： A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.

摘要翻译： 记忆系统包括分为子银行或子银行集合的逻辑银行。 存储器系统通过顺序地访问子银行或子银行集合来响应指向给定逻辑银行的存储器访问请求（例如，读取和写入）。 顺序访问减少了由存储器操作引起的电源尖峰的影响，从而有助于提高系统性能。 存储器系统的一些实施例将顺序的子银行访问与诸如更宽的电源总线或增加的旁路电容的其他性能增强特征相结合，以进一步提高性能。

公开(公告)号：US20080062807A1

公开(公告)日：2008-03-13

申请号：US11853708

申请日：2007-09-11

申请人： Frederick Ware ,  Lawrence Lai ,  Chad Bellows ,  Wayne Richardson

发明人： Frederick Ware ,  Lawrence Lai ,  Chad Bellows ,  Wayne Richardson

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。

公开(公告)号：US20060117155A1

公开(公告)日：2006-06-01

申请号：US10998402

申请日：2004-11-29

申请人： Frederick Ware ,  Craig Hampel ,  Wayne Richardson ,  Chad Bellows ,  Lawrence Lai

发明人： Frederick Ware ,  Craig Hampel ,  Wayne Richardson ,  Chad Bellows ,  Lawrence Lai

IPC分类号： G06F12/14

CPC分类号： G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

公开(公告)号：US20060072366A1

公开(公告)日：2006-04-06

申请号：US10955193

申请日：2004-09-30

申请人： Frederick Ware ,  Lawrence Lai ,  Chad Bellows ,  Wayne Richardson

发明人： Frederick Ware ,  Lawrence Lai ,  Chad Bellows ,  Wayne Richardson

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。 响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。 第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。 第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。

公开(公告)号：US20110211415A1

公开(公告)日：2011-09-01

申请号：US13103548

申请日：2011-05-09

申请人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

发明人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

摘要翻译： 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：US08391099B2

公开(公告)日：2013-03-05

申请号：US13103548

申请日：2011-05-09

申请人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

发明人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC分类号： G11C8/18

CPC分类号： G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

摘要翻译： 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：US07940598B2

公开(公告)日：2011-05-10

申请号：US12177357

申请日：2008-07-22

申请人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

发明人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC分类号： G11C8/00

CPC分类号： G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

摘要翻译： 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：US20080279032A1

公开(公告)日：2008-11-13

申请号：US12177357

申请日：2008-07-22

申请人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

发明人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC分类号： G11C8/10

CPC分类号： G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

摘要翻译： 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。