Calibration method and circuit
    1.
    发明授权
    Calibration method and circuit 有权
    校准方法和电路

    公开(公告)号:US08576102B2

    公开(公告)日:2013-11-05

    申请号:US13310932

    申请日:2011-12-05

    IPC分类号: H03M1/10

    CPC分类号: H03M1/1038 H03M1/46

    摘要: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.

    摘要翻译: 对模拟输入信号进行采样,并将采样的模拟输入信号转换为数字值。 还对采样的校准值进行采样,并根据采样的校准值计算N位偏移值的单个位。 替代地执行采样操作,使得针对每个产生的数字值产生偏移值的一个位。 例如,该过程重复N次以计算偏移值的所有N位,同时生成N个数字值。

    Method for adaptive biasing of fully differential gain boosted operational amplifiers
    2.
    发明授权
    Method for adaptive biasing of fully differential gain boosted operational amplifiers 有权
    全差分增益增益运算放大器的自适应偏置方法

    公开(公告)号:US07852159B2

    公开(公告)日:2010-12-14

    申请号:US12178769

    申请日:2008-07-24

    IPC分类号: H03F3/45

    摘要: An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB).

    摘要翻译: 自适应偏置技术可以完全提高差分增益提升运算放大器的瞬态特性并降低功耗。 自适应偏置模块包括偏置生成模块和偏置复制模块。 偏置产生模块产生第一控制信号(VCMNB),并且将第一控制信号作为差分增强器的输出共模(偏置复制模块内部)施加。 偏置复制模块耦合到偏置产生模块,用于利用第一控制信号(VCMNB)对差分升压器的共模进行均衡。

    METHOD FOR ADAPTIVE BIASING OF FULLY DIFFERENTIAL GAIN BOOSTED OPERATIONAL AMPLIFIERS
    3.
    发明申请
    METHOD FOR ADAPTIVE BIASING OF FULLY DIFFERENTIAL GAIN BOOSTED OPERATIONAL AMPLIFIERS 有权
    全面差分增益运算放大器自适应偏置的方法

    公开(公告)号:US20090027126A1

    公开(公告)日:2009-01-29

    申请号:US12178769

    申请日:2008-07-24

    IPC分类号: H03F3/45

    摘要: An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB).

    摘要翻译: 自适应偏置技术可以完全提高差分增益提升运算放大器的瞬态特性并降低功耗。 自适应偏置模块包括偏置生成模块和偏置复制模块。 偏置产生模块产生第一控制信号(VCMNB),并且将第一控制信号作为差分增强器的输出共模(偏置复制模块内部)施加。 偏置复制模块耦合到偏置产生模块,用于利用第一控制信号(VCMNB)对差分升压器的共模进行均衡。

    DIFFERENTIAL SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER
    4.
    发明申请
    DIFFERENTIAL SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER 有权
    数字转换器的差分逼近逼近模拟

    公开(公告)号:US20120139771A1

    公开(公告)日:2012-06-07

    申请号:US13166117

    申请日:2011-06-22

    IPC分类号: H03M1/12

    CPC分类号: H03M1/468

    摘要: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

    摘要翻译: 一种差分逐次逼近模数转换器,包括:比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器,所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器,所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量,其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个:第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路,其适于在采样阶段期间对差分输入电压进行采样,并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。

    Bistable CML Circuit
    5.
    发明申请
    Bistable CML Circuit 有权
    双稳态CML电路

    公开(公告)号:US20110316587A1

    公开(公告)日:2011-12-29

    申请号:US13166608

    申请日:2011-06-22

    IPC分类号: H03K5/22

    摘要: A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.

    摘要翻译: 一种公共源电路,包括在施加电压的端子和电流源之间并联的两个分支,每个分支包括:电阻器和晶体管的串联关联,其连接点限定所述分支的输出端子; 将所述分支的输入端子连接到所述晶体管的控制端子的第一开关; 以及用于放大表示相对分支的输出端子上存在的电平的数据的可控级。

    Compact SAR ADC
    6.
    发明授权
    Compact SAR ADC 有权
    紧凑型SAR ADC

    公开(公告)号:US08514123B2

    公开(公告)日:2013-08-20

    申请号:US13247001

    申请日:2011-09-28

    IPC分类号: H03M1/34

    CPC分类号: H03M1/468

    摘要: A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.

    摘要翻译: 一种逐次逼近模数转换的方法,包括:在采样阶段期间,将输入信号耦合到多对电容器; 并且在转换阶段期间,将每对的第一电容器耦合到第一电源电压,将每对的第二电容器耦合到第二电源电压。

    Circuit for Generating a Reference Voltage Under a Low Power Supply Voltage
    7.
    发明申请
    Circuit for Generating a Reference Voltage Under a Low Power Supply Voltage 审中-公开
    在低电源电压下产生参考电压的电路

    公开(公告)号:US20120153997A1

    公开(公告)日:2012-06-21

    申请号:US13242508

    申请日:2011-09-23

    IPC分类号: H03B1/00

    CPC分类号: G05F3/30

    摘要: A circuit for generating a reference voltage including: a first current source in series with a first bipolar transistor, between a first and a second terminal of application of a power supply voltage; a second current source in series with a second bipolar transistor and a first resistive element, between said first and second terminals, the junction point of the first resistive element and of the second bipolar transistor defining a third terminal for providing the reference voltage; a follower assembly having an input terminal connected between the first current source and the first bipolar transistor, and having an output terminal connected to a base of the second bipolar transistor; and a resistive dividing bridge between the output terminal of the follower assembly and said second terminal, the midpoint of this dividing bridge being connected to a base of the first bipolar transistor.

    摘要翻译: 一种用于产生参考电压的电路,包括:与第一双极晶体管串联的第一电流源,在施加电源电压的第一和第二端子之间; 与所述第一和第二端子之间的第二双极晶体管和第一电阻元件串联的第二电流源,所述第一电阻元件和所述第二双极晶体管的结点限定用于提供参考电压的第三端子; 跟随器组件,其具有连接在第一电流源和第一双极晶体管之间的输入端子,并且具有连接到第二双极晶体管的基极的输出端子; 以及在从动组件的输出端子和所述第二端子之间的电阻分压桥,该分隔桥的中点连接到第一双极晶体管的基极。

    COMPACT SAR ADC
    8.
    发明申请

    公开(公告)号:US20120112948A1

    公开(公告)日:2012-05-10

    申请号:US13247001

    申请日:2011-09-28

    IPC分类号: H03M1/12

    CPC分类号: H03M1/468

    摘要: A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.

    摘要翻译: 一种逐次逼近模数转换的方法,包括:在采样阶段期间,将输入信号耦合到多对电容器; 并且在转换阶段期间,将每对的第一电容器耦合到第一电源电压,将每对的第二电容器耦合到第二电源电压。

    Differential successive approximation analog to digital converter
    9.
    发明授权
    Differential successive approximation analog to digital converter 有权
    差分逐次逼近模数转换器

    公开(公告)号:US08497795B2

    公开(公告)日:2013-07-30

    申请号:US13166117

    申请日:2011-06-22

    IPC分类号: H03M1/34

    CPC分类号: H03M1/468

    摘要: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

    摘要翻译: 一种差分逐次逼近模数转换器,包括:比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器,所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器,所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量,其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个:第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路,其适于在采样阶段期间对差分输入电压进行采样,并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。

    Bistable CML circuit
    10.
    发明授权
    Bistable CML circuit 有权
    双稳态CML电路

    公开(公告)号:US08378727B2

    公开(公告)日:2013-02-19

    申请号:US13166608

    申请日:2011-06-22

    IPC分类号: H03K3/00

    摘要: A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.

    摘要翻译: 一种公共源电路,包括在施加电压的端子和电流源之间并联的两个分支,每个分支包括:电阻器和晶体管的串联关联,其连接点限定所述分支的输出端子; 将所述分支的输入端子连接到所述晶体管的控制端子的第一开关; 以及用于放大表示相对分支的输出端子上存在的电平的数据的可控级。