公开(公告)号：US20140065811A1

公开(公告)日：2014-03-06

申请号：US13603726

申请日：2012-09-05

申请人： Chang Seo Park ,  Vimal K. Kamineni

发明人： Chang Seo Park ,  Vimal K. Kamineni

IPC分类号： H01L29/40

CPC分类号： H01L29/401 ,  H01L29/66545 ,  H01L29/66795

摘要： Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.

摘要翻译： 本发明的实施例涉及使用低电阻率金属（例如W）作为替代间隙填充金属形成RMG FinFET半导体器件的方法。 具体地，半导体通常将包括形成在衬底上以形成一个或多个沟槽（例如，短/窄和/或长/宽沟槽/沟道）的一组（例如，一个或多个）电介质叠层。 工作功能层（例如，TiN）将被提供在衬底上（例如，在沟槽中和周围）。 然后可以沉积低电阻金属栅极层（例如，W）（例如通过化学气相沉积）并抛光（例如，经由化学机械抛光）。 此后，可以在抛光之后蚀刻栅极金属层和功函数层，以沿着其底表面在蚀刻的功函数层上方提供具有蚀刻的栅极金属层的沟槽。

公开(公告)号：US08722491B2

公开(公告)日：2014-05-13

申请号：US13603726

申请日：2012-09-05

申请人： Chang Seo Park ,  Vimal K. Kamineni

发明人： Chang Seo Park ,  Vimal K. Kamineni

IPC分类号： H01L21/8234 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/44

CPC分类号： H01L29/401 ,  H01L29/66545 ,  H01L29/66795

摘要： Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.

摘要翻译： 本发明的实施例涉及使用低电阻率金属（例如W）作为替代间隙填充金属形成RMG FinFET半导体器件的方法。 具体地，半导体通常将包括形成在衬底上以形成一个或多个沟槽（例如，短/窄和/或长/宽沟槽/沟道）的一组（例如，一个或多个）电介质叠层。 工作功能层（例如，TiN）将被提供在衬底上（例如，在沟槽中和周围）。 然后可以沉积低电阻金属栅极层（例如，W）（例如通过化学气相沉积）并抛光（例如，经由化学机械抛光）。 此后，可以在抛光之后蚀刻栅极金属层和功函数层，以沿着其底表面在蚀刻的功函数层上方提供具有蚀刻的栅极金属层的沟槽。

公开(公告)号：US20130043592A1

公开(公告)日：2013-02-21

申请号：US13213449

申请日：2011-08-19

申请人： Chang Seo Park ,  Jin Cho

发明人： Chang Seo Park ,  Jin Cho

IPC分类号： H01L29/49 ,  H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/7833

摘要： Disclosed herein are various methods of forming a replacement gate comprised of silicon and various semiconductor devices incorporation such a replacement gate structure. In one example, the method includes removing a sacrificial gate electrode structure to define a gate opening, forming a replacement gate structure in the gate opening, the replacement gate structure including at least one metal layer and a silicon-containing gate structure that is at least partially made of a metal silicide and forming a protective layer above at least a portion of the replacement gate structure.

摘要翻译： 本文公开了形成由硅构成的替代栅极和结合这种替代栅极结构的各种半导体器件的各种方法。 在一个示例中，该方法包括去除牺牲栅极电极结构以限定栅极开口，在栅极开口中形成替代栅极结构，所述替换栅极结构至少包括一个金属层和至少含有硅的栅极结构 部分地由金属硅化物制成并在替代栅极结构的至少一部分上方形成保护层。

公开(公告)号：US20130005131A1

公开(公告)日：2013-01-03

申请号：US13174257

申请日：2011-06-30

申请人： Chang Seo Park

发明人： Chang Seo Park

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823842

摘要： Methods is provided for forming a CMOS device. The method includes providing a substrate and depositing a gate stack on the substrate. The gate stack includes a gate dielectric and a dummy gate including polycrystalline silicon (polySi). The method also includes depositing a dielectric layer on the substrate after depositing the gate stack on the substrate. The method further includes substituting the dummy gate with a metal without first removing the dummy gate.

摘要翻译： 提供了用于形成CMOS器件的方法。 该方法包括提供衬底并在衬底上沉积栅叠层。 栅极堆叠包括栅极电介质和包括多晶硅（polySi）的虚拟栅极。 该方法还包括在将栅极堆叠沉积在衬底上之后，在衬底上沉积电介质层。 该方法还包括在没有首先去除虚拟栅极的情况下用金属代替虚拟栅极。

公开(公告)号：US07316950B2

公开(公告)日：2008-01-08

申请号：US10826665

申请日：2004-04-16

申请人： Chang Seo Park ,  Byung Jin Cho ,  Narayanan T. Balasubramanian

发明人： Chang Seo Park ,  Byung Jin Cho ,  Narayanan T. Balasubramanian

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/517 ,  H01L29/518

摘要： A method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AINx) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.

摘要翻译： 一种构造双金属栅极CMOS结构的方法，其在处理期间在金属栅极和栅极电介质之间使用超薄氮化铝（AlN x×x））缓冲层，以防止栅极电介质暴露在金属中 蚀刻工艺。 在不需要的栅极金属被蚀刻掉之后，CMOS结构退火。 在退火过程中，缓冲层通过与金属栅极的反应而完全消耗，并形成新的金属合金，导致等效氧化物厚度的最小增加。 缓冲层和栅极金属在确定金属/电介质界面的功函数方面发挥关键作用，因为原始栅极金属的功函数作为退火过程的结果而被修改。

公开(公告)号：US06964952B2

公开(公告)日：2005-11-15

申请号：US10662002

申请日：2003-09-12

申请人： Chang Seo Park ,  Jin Wook Kim ,  Jin Hee Choi ,  Ui Chan Koh

发明人： Chang Seo Park ,  Jin Wook Kim ,  Jin Hee Choi ,  Ui Chan Koh

IPC分类号： A61K31/047 ,  A61K31/133 ,  A61K31/66

CPC分类号： A61K31/047 ,  A61K31/133 ,  A61K31/66 ,  Y10S514/88 ,  Y10S514/882 ,  A61K2300/00

摘要： The invention relates to a therapeutic composition for broad spectrum dermal disease and in particular, to a composition comprising principal lipid components of skin, preferably having about 30 to 90% by weight of a carrier for applying to skin; 0.01 to 5.0% by weight of sphingolipid long-chain base; 0.001 to 1.0% by weight of lysophosphatidic acid; and 1 to 40% by weight of organic or inorganic additives. The composition is useful for the treatment and improvement of atopic dermatitis, psoriasis, acne, ichthyosis, infectious dermatitis, pruritus, erythema derived from pruritus, vulnus, chapping of skin and ulcer, etc.

摘要翻译： 本发明涉及用于广谱皮肤病的治疗组合物，特别涉及一种包含皮肤主要脂质组分的组合物，优选具有约30至90重量％的施用于皮肤的载体; 0.01〜5.0％重量的鞘脂长链碱; 0.001至1.0重量％的溶血磷脂酸; 和1至40重量％的有机或无机添加剂。 该组合物可用于治疗和改善特应性皮炎，牛皮癣，痤疮，鱼鳞病，感染性皮炎，瘙痒，源自瘙痒，外阴，皮肤和溃疡等的红斑等。

公开(公告)号：US08409466B2

公开(公告)日：2013-04-02

申请号：US12880873

申请日：2010-09-13

申请人： Chang Seo Park

发明人： Chang Seo Park

IPC分类号： C09K5/00

CPC分类号： C09K5/10 ,  C23C30/00 ,  C23F11/08 ,  C23F11/182

摘要： A composition comprising at least one ionized silicate mineral and water, wherein the at least one ionized silicate mineral is solvated in water, and wherein decomposition comprises an ionized germanium dioxide, its method of making, and its method of using are disclosed. While the composition is subject to a wide range of applications, it is especially suited for use in a coolant system for a combustion engine, and in particular, the coolant system for an internal combustion engine for vehicles.

摘要翻译： 一种包含至少一种离子化硅酸盐矿物和水的组合物，其中所述至少一种离子化硅酸盐矿物质溶解在水中，并且其中分解包括电离二氧化锗，其制备方法及其使用方法。 虽然组合物受到广泛的应用，但是它特别适用于用于内燃机的冷却剂系统，特别是用于车辆的内燃机的冷却剂系统。

公开(公告)号：US06551913B1

公开(公告)日：2003-04-22

申请号：US09343480

申请日：1999-06-30

申请人： Hyeon Soo Kim ,  Chang Seo Park

发明人： Hyeon Soo Kim ,  Chang Seo Park

IPC分类号： H01L213205

CPC分类号： H01L29/665

摘要： The present invention relates to a semiconductor technology and more specifically to a method of fabricating a gate electrode of a semiconductor device, where a re-oxidation process that may cause an abnormal oxidation can be eliminated. In a polysilicon/silicide structure or polysilicon/metal structure of gate electrode, a step of etching side parts of gate electrode is performed without any etch mask after gate patterning. Here, the etch can be made by wet or dry etch using an etchant having high selectivity of polysilicon film to a gate oxide film, so that the damaged gate oxide part during the gate patterning is allowed not to make a role of the gate insulating film itself, thereby eliminating the re-oxidation process.

摘要翻译： 本发明涉及一种半导体技术，更具体地涉及制造可能引起异常氧化的再氧化工艺的半导体器件的栅电极的制造方法。 在栅极电极的多晶硅/硅化物结构或多晶硅/金属结构中，在栅极图案化之后，没有任何蚀刻掩模执行刻蚀栅极的侧面部分的步骤。 这里，可以通过使用具有多晶硅膜对栅极氧化膜的高选择性的蚀刻剂的湿蚀刻或干法蚀刻来进行蚀刻，使得栅极图案化期间损坏的栅极氧化物部分不被起到栅极绝缘膜的作用 本身，从而消除再氧化过程。

公开(公告)号：US06194196B1

公开(公告)日：2001-02-27

申请号：US09329999

申请日：1999-06-11

申请人： Chang Seo Park ,  Ji Hean Jeong ,  Sung Yong Hong ,  Woo Seok Choi

发明人： Chang Seo Park ,  Ji Hean Jeong ,  Sung Yong Hong ,  Woo Seok Choi

IPC分类号： C12N114

CPC分类号： C12P13/02 ,  C12R1/84 ,  Y10S435/938

摘要： The present invention relates to a microbiological process for preparing sphingolipids, especially, tetraacetylphytosphingosine(TAPS), using novel yeast cell Pichia ciferrii DSCC 7-25 under optimal fermentation conditions. Further, this invention concerns a novel yeast cell Pichia ciferrii DSCC 7-25 and it's isolation method from wild type of Pichia ciferrii strain.

摘要翻译： 本发明涉及在最佳发酵条件下使用新型酵母细胞毕赤酵母DSCC 7-25制备鞘脂，特别是四乙酰鸟嘌呤（TAPS）的微生物学方法。 此外，本发明涉及一种新型酵母细胞毕赤酵母DSCC7-25，其是野生型毕赤酵母菌株的分离方法。

公开(公告)号：US5994238A

公开(公告)日：1999-11-30

申请号：US769520

申请日：1996-12-19

申请人： Chang Seo Park

发明人： Chang Seo Park

IPC分类号： H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311

CPC分类号： H01L21/31116

摘要： A method for fabricating a semiconductor device is characterized by using a mixture chemical comprising ozone gas, anhydrous HF gas and deionized water vapor as an etchant for etching an oxide- and silicon-exposed wafer, whereby the etch selection ratio of oxide to silicon can be controlled according to necessity, so that the production yield and reliability of semiconductor device are improved. During etching of a wafer with exposed thermal oxide and exposed silicon, the etch rate ratio of oxide to silicon is controlled by changing the relative flow rates of the ozone gas, anhydrous HF gas and deionized water vapor.

摘要翻译： 一种制造半导体器件的方法的特征在于使用包含臭氧气体，无水HF气体和去离子水蒸汽的混合物化学品作为用于蚀刻氧化物和硅暴露晶片的蚀刻剂，由此氧化物与硅的蚀刻选择比可以是 根据需要进行控制，提高了半导体器件的生产成本和可靠性。 在具有暴露的热氧化物和暴露的硅的晶片的蚀刻期间，通过改变臭氧气体，无水HF气体和去离子水蒸气的相对流速来控制氧化物到硅的蚀刻速率比。