公开(公告)号：US07692960B2

公开(公告)日：2010-04-06

申请号：US11641992

申请日：2006-12-20

Applicant: Chang-Ting Chen ,  Chun-Jen Huang

Inventor： Chang-Ting Chen ,  Chun-Jen Huang

IPC: G11C7/00

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/3409

Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Abstract translation: 一种用于改善电荷俘获存储单元的擦除效果的方法。 电荷捕获存储单元具有晶体管，其具有耦合到第一位线的第一端子和耦合到第二位线的第二端子。 首先，该方法擦除电荷捕获存储单元。 然后，在电荷捕获存储单元被完全擦除之后，第一位线电连接到第二位线，以使第一位线的电压电平等于第二位线的电压电平，使得第 晶体管的第一端子等于晶体管的第二端子的电压电平。

公开(公告)号：US20080151620A1

公开(公告)日：2008-06-26

申请号：US11641992

申请日：2006-12-20

Applicant: Chang-Ting Chen ,  Chun-Jen Huang

Inventor： Chang-Ting Chen ,  Chun-Jen Huang

IPC: G11C16/14

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/3409

Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Abstract translation: 一种用于改善电荷俘获存储单元的擦除效果的方法。 电荷捕获存储单元具有晶体管，其具有耦合到第一位线的第一端子和耦合到第二位线的第二端子。 首先，该方法擦除电荷捕获存储单元。 然后，在电荷捕获存储单元被完全擦除之后，第一位线电连接到第二位线，以使第一位线的电压电平等于第二位线的电压电平，使得第 晶体管的第一端子等于晶体管的第二端子的电压电平。

公开(公告)号：US20130285737A1

公开(公告)日：2013-10-31

申请号：US13460112

申请日：2012-04-30

Applicant: Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

Inventor： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

IPC: G05F3/02

CPC classification number: H02M3/07

Abstract: In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

Abstract translation: 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

公开(公告)号：US20080171433A1

公开(公告)日：2008-07-17

申请号：US11621996

申请日：2007-01-11

Applicant: Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

Inventor： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC: H01L21/768

CPC classification number: H01L21/76811

Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

Abstract translation: 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF 4 N 3 N 3等离子体从双镶嵌开口选择性地去除暴露的盖层。

公开(公告)号：US07378343B2

公开(公告)日：2008-05-27

申请号：US11164285

申请日：2005-11-17

Applicant: Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

Inventor： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC: H01L21/4763

CPC classification number: H01L21/7681 ,  H01L21/76829

Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

Abstract translation: 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

公开(公告)号：US20070210454A1

公开(公告)日：2007-09-13

申请号：US11748472

申请日：2007-05-14

Applicant: Pei-Yu Chou ,  Chun-Jen Huang

Inventor： Pei-Yu Chou ,  Chun-Jen Huang

IPC: H01L23/52

CPC classification number: H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

Abstract: A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Abstract translation: 用于金属互连的工艺和结构包括：使用第一图案化硬掩模提供具有第一电导体，形成第一介电层和第一图案化硬掩模的基板，以形成第一开口和第二导电体，形成第二导体 电介质层和第二图案化硬掩模，使用第二图案化硬掩模作为蚀刻掩模，并使用第一图案化硬掩模作为蚀刻停止层以形成第二开口和第三导电体。

公开(公告)号：US20070125750A1

公开(公告)日：2007-06-07

申请号：US11674678

申请日：2007-02-14

Applicant: Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

Inventor： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

IPC: C23F1/00 ,  H01L21/302 ,  B44C1/22

CPC classification number: H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues.

Abstract translation: 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。

公开(公告)号：US20070111514A1

公开(公告)日：2007-05-17

申请号：US11164285

申请日：2005-11-17

Applicant: Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

Inventor： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC: H01L21/473

CPC classification number: H01L21/7681 ,  H01L21/76829

Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

Abstract translation: 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

公开(公告)号：US08080877B2

公开(公告)日：2011-12-20

申请号：US12821136

申请日：2010-06-23

Applicant: Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

Inventor： Chun-Jen Huang ,  Yu-Tsung Lai ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76811

Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

Abstract translation: 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。

公开(公告)号：US20110248747A1

公开(公告)日：2011-10-13

申请号：US13081472

申请日：2011-04-06

Applicant: Chun-Jen Huang

Inventor： Chun-Jen Huang

IPC: H02M1/00

CPC classification number: G05F3/30

Abstract: General speaking, a resistor of high resistivity has a negative-temperature-coefficient and a resistor of low resistivity has a positive-temperature-coefficient. Utilizing this characteristic, an appropriate proportion between the above resistors can be found to make a combined resistor with an approximate zero-temperature-coefficient. The combined resistor can be used to design a circuit for generating voltage and current with approximate zero-temperature-coefficients.

Abstract translation: 一般来说，高电阻率的电阻器具有负温度系数，低电阻率的电阻器具有正温度系数。 利用该特性，可以发现上述电阻器之间的适当比例使得具有近似零温度系数的组合电阻器。 组合电阻器可用于设计用于产生具有近似零温度系数的电压和电流的电路。