公开(公告)号：US07692960B2

公开(公告)日：2010-04-06

申请号：US11641992

申请日：2006-12-20

Applicant: Chang-Ting Chen ,  Chun-Jen Huang

Inventor： Chang-Ting Chen ,  Chun-Jen Huang

IPC: G11C7/00

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/3409

Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Abstract translation: 一种用于改善电荷俘获存储单元的擦除效果的方法。 电荷捕获存储单元具有晶体管，其具有耦合到第一位线的第一端子和耦合到第二位线的第二端子。 首先，该方法擦除电荷捕获存储单元。 然后，在电荷捕获存储单元被完全擦除之后，第一位线电连接到第二位线，以使第一位线的电压电平等于第二位线的电压电平，使得第 晶体管的第一端子等于晶体管的第二端子的电压电平。

公开(公告)号：US20080151620A1

公开(公告)日：2008-06-26

申请号：US11641992

申请日：2006-12-20

Applicant: Chang-Ting Chen ,  Chun-Jen Huang

Inventor： Chang-Ting Chen ,  Chun-Jen Huang

IPC: G11C16/14

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/3409

Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Abstract translation: 一种用于改善电荷俘获存储单元的擦除效果的方法。 电荷捕获存储单元具有晶体管，其具有耦合到第一位线的第一端子和耦合到第二位线的第二端子。 首先，该方法擦除电荷捕获存储单元。 然后，在电荷捕获存储单元被完全擦除之后，第一位线电连接到第二位线，以使第一位线的电压电平等于第二位线的电压电平，使得第 晶体管的第一端子等于晶体管的第二端子的电压电平。

公开(公告)号：US20130242665A1

公开(公告)日：2013-09-19

申请号：US13536555

申请日：2012-06-28

Applicant: Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

IPC: G11C16/16

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/14 ,  G11C29/34 ,  G11C2029/2602

Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

Abstract translation: 非易失性存储器阵列具有不同持续时间的多个擦除过程。 可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

公开(公告)号：US08797802B2

公开(公告)日：2014-08-05

申请号：US13536555

申请日：2012-06-28

Applicant: Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

IPC: G11C11/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/14 ,  G11C29/34 ,  G11C2029/2602

Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

Abstract translation: 非易失性存储器阵列具有不同持续时间的多个擦除过程。 可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

公开(公告)号：US20060262634A1

公开(公告)日：2006-11-23

申请号：US11132635

申请日：2005-05-19

Applicant: Chi-Ming Chen ,  Chang-Ting Chen

Inventor： Chi-Ming Chen ,  Chang-Ting Chen

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: In one embodiment, a memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further includes a row decoder attached to the multiple word lines. The row decoder is operable to assert and to de-assert individual word lines. Each of the word lines has a head portion adjacent to where the word line is attached to the row decoder. The memory device supports a column decode sequence for accessing multiple storage cells within a row of the array. The column decode sequence both commences and terminates at or near the head portion of the word line corresponding to the row.

Abstract translation: 在一个实施例中，存储器设备包括存储单元阵列，多个字线，其中每个字线对应于存储单元阵列中的一行，以及多个位线，其中每个位线对应于阵列中的列 存储单元。 该设备还包括附加到多个字线的行解码器。 行解码器可操作来断言和取消断言单个字线。 每个字线具有与字线附接到行解码器的位置相邻的头部。 该存储器件支持用于访问该阵列的一行内的多个存储单元的列解码序列。 列解码序列都开始并终止于对应于行的字线的头部或附近。

公开(公告)号：US07391672B1

公开(公告)日：2008-06-24

申请号：US11645708

申请日：2006-12-27

Applicant: Chang-Ting Chen ,  Chung-Kuang Chen

Inventor： Chang-Ting Chen ,  Chung-Kuang Chen

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/1018 ,  G11C16/0491 ,  G11C16/26 ,  G11C17/126 ,  G11C2207/005

Abstract: A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage levels of the first and second terminals of the nth transistor are respectively transformed into a source voltage and a drain voltage in an nth reading period, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage, wherein n is a positive integer smaller than m. Thereafter, the voltage levels of the first and second terminals of the mth transistor are respectively transformed into the source voltage and the drain voltage in an mth reading period. The source voltage equals the ground voltage.

Abstract translation: 一种顺序访问存储器的方法。 存储器具有（m + 1）位线和至少一行晶体管，其中m是正整数。 该方法包括以下步骤。 首先，晶体管的第一和第二端子的电压电平在预放电时段内与地电压相等。 接下来，第n 晶体管的第一端子和第二端子的电压电平分别在第n 读取周期中变换为源极电压和漏极电压，并且 （n + 1）^{晶体管的第二端子的电压电平变换为隔离电压，其中n是小于m的正整数。 此后，在第m个读取周期中，第m个/或者以上晶体管的第一和第二端子的电压电平分别变换为源极电压和漏极电压。 源极电压等于接地电压。}

公开(公告)号：US07379363B2

公开(公告)日：2008-05-27

申请号：US11692108

申请日：2007-03-27

Applicant: Chang-Ting Chen

Inventor： Chang-Ting Chen

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C2207/2236 ,  G11C2207/2245

Abstract: Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met which does not allow time for precharging a second word line.

Abstract translation: 各种方法和装置允许高速读取存储器。 数据部分被复制并存储在其他字线上。 通过读取存储在已经被预充电的字线访问的存储器单元上的数据的副本，可以满足延迟规定，这不允许用于预充电第二字线的时间。

公开(公告)号：US07209406B2

公开(公告)日：2007-04-24

申请号：US11132635

申请日：2005-05-19

Applicant: Chi-Ming Chen ,  Chang-Ting Chen

Inventor： Chi-Ming Chen ,  Chang-Ting Chen

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: A memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further includes a row decoder attached to the multiple word lines. The row decoder is operable to assert and to de-assert individual word lines. Each of the word lines has a head portion adjacent to where the word line is attached to the row decoder. The memory device supports a column decode sequence for accessing multiple storage cells within a row of the array. The column decode sequence both commences and terminates at or near the head portion of the word line corresponding to the row.

Abstract translation: 存储器件包括存储单元阵列，多个字线，其中每个字线对应于存储单元阵列中的一行，以及多个位线，其中每个位线对应于存储单元阵列中的列。 该设备还包括附加到多个字线的行解码器。 行解码器可操作来断言和取消断言单个字线。 每个字线具有与字线附接到行解码器的位置相邻的头部。 该存储器件支持用于访问该阵列的一行内的多个存储单元的列解码序列。 列解码序列都开始并终止于对应于行的字线的头部或附近。

公开(公告)号：US20060262616A1

公开(公告)日：2006-11-23

申请号：US11131580

申请日：2005-05-18

Applicant: Chang-Ting Chen

Inventor： Chang-Ting Chen

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C2207/2236 ,  G11C2207/2245

Abstract: Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met which does not allow time for precharging a second word line.

Abstract translation: 各种方法和装置允许高速读取存储器。 数据部分被复制并存储在其他字线上。 通过读取存储在已经被预充电的字线访问的存储器单元上的数据的副本，可以满足延迟规定，这不允许用于预充电第二字线的时间。

公开(公告)号：US08723559B2

公开(公告)日：2014-05-13

申请号：US13603815

申请日：2012-09-05

Applicant: Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

Inventor： Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: H03B1/00 ,  H03K3/00

CPC classification number: G11C8/08 ,  G11C16/08

Abstract: A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.

Abstract translation: 可用作字线驱动器的电路包括响应于控制节点上的电压而切换的驱动器，以及向控制节点提供电压的电路。 向控制节点施加电压的电路提供趋向于将控制节点拉至第一源电压的第一静态电流，并且响应于选择驱动器的信号提供战斗电流脉冲以将控制节点向下拉到第二静态电流 源电压，克服第一静电流。 此外，电路在选择驱动器的信号转变时提供上拉升压电流，该信号使关闭电流消失，并且向控制节点施加升压电流脉冲，以帮助快速将控制节点拉到第一源电压 。