公开(公告)号：US08279007B2

公开(公告)日：2012-10-02

申请号：US12995279

申请日：2010-10-21

申请人： ChangMing Wei ,  Yu Zhang ,  Lixin Jiang ,  JinFu Chen ,  Jeffrey G. Barrow

发明人： ChangMing Wei ,  Yu Zhang ,  Lixin Jiang ,  JinFu Chen ,  Jeffrey G. Barrow

IPC分类号： H03G3/30

CPC分类号： H03F3/45475 ,  H03F2203/45534 ,  H03F2203/45536 ,  H03G1/0088 ,  H03K17/063 ,  H03K17/6872 ,  H03K17/6877 ,  H03K2017/066 ,  H03K2217/0054

摘要： A switch circuit is provided. The switch circuit may include a first transistor having a source terminal to accept an input signal, a drain terminal to provide an output signal, and a gate; a power supply providing a gate voltage. The switch circuit may also include a circuit to couple a switch signal to the gate, wherein the circuit turns the first transistor ‘off’ for all values of the input signal when the switch signal is ‘low.’ A programmable gain amplifier (PGA) is also provided. The PGA may include an input stage having an input node to couple an input signal, and an output node to provide a gate signal, at least a first gain stage including a resistor and a switch circuit as above. A differential gain amplifier may be included to provide an output signal from the gain signal.

摘要翻译： 提供开关电路。 开关电路可以包括具有用于接收输入信号的源极端子的第一晶体管，提供输出信号的漏极端子和栅极; 提供栅极电压的电源。 开关电路还可以包括用于将开关信号耦合到栅极的电路，其中当开关信号为低时，该电路关闭所有输入信号值。 还提供可编程增益放大器（PGA）。 PGA可以包括输入级，其具有用于耦合输入信号的输入节点和输出节点以提供门信号，至少第一增益级包括如上所述的电阻器和开关电路。 可以包括差分增益放大器以从增益信号提供输出信号。

公开(公告)号：US20120098597A1

公开(公告)日：2012-04-26

申请号：US12995279

申请日：2010-10-21

申请人： ChangMing Wei ,  Yu Zhang ,  Lixin Jiang ,  Jin Fu Chen ,  Jeffrey G. Barrow

发明人： ChangMing Wei ,  Yu Zhang ,  Lixin Jiang ,  Jin Fu Chen ,  Jeffrey G. Barrow

IPC分类号： H03F3/45 ,  H03K17/687

CPC分类号： H03F3/45475 ,  H03F2203/45534 ,  H03F2203/45536 ,  H03G1/0088 ,  H03K17/063 ,  H03K17/6872 ,  H03K17/6877 ,  H03K2017/066 ,  H03K2217/0054

摘要： A switch circuit is provided. The switch circuit may include a first transistor having a source terminal to accept an input signal, a drain terminal to provide an output signal, and a gate; a power supply providing a gate voltage. The switch circuit may also include a circuit to couple a switch signal to the gate, wherein the circuit turns the first transistor ‘off’ for all values of the input signal when the switch signal is ‘low.’ A programmable gain amplifier (PGA) is also provided. The PGA may include an input stage having an input node to couple an input signal, and an output node to provide a gate signal, at least a first gain stage including a resistor and a switch circuit as above. A differential gain amplifier may be included to provide an output signal from the gain signal.

摘要翻译： 提供开关电路。 开关电路可以包括具有用于接收输入信号的源极端子的第一晶体管，提供输出信号的漏极端子和栅极; 提供栅极电压的电源。 开关电路还可以包括用于将开关信号耦合到栅极的电路，其中当开关信号为“低”时，该电路使第一晶体管关断输入信号的所有值。可编程增益放大器（PGA） 也提供。 PGA可以包括输入级，其具有用于耦合输入信号的输入节点和输出节点以提供门信号，至少第一增益级包括如上所述的电阻器和开关电路。 可以包括差分增益放大器以从增益信号提供输出信号。

公开(公告)号：US20120235241A1

公开(公告)日：2012-09-20

申请号：US13048726

申请日：2011-03-15

申请人： Jeffrey G. Barrow

发明人： Jeffrey G. Barrow

IPC分类号： H01L27/088 ,  G06F17/50

CPC分类号： H01L27/088 ,  H01L27/0207

摘要： A power transistor and a power converter are disclosed that may improve the on-resistance and corresponding silicon area of a power transistor. The power transistor may comprise a drain, a source, and a channel therebetween divided into a plurality of transistor stripes, the plurality of transistor stripes being grouped in a plurality of different groups. The power transistor may further comprise a first top metal associated with one of the drain and the source, and a second top metal associated with the other of the drain and the source. The second top metal includes at least one portion that is coupled to different groups of transistor stripes. A related method for determining a layout topology of a power transistor is also disclosed.

摘要翻译： 公开了功率晶体管和功率转换器，其可以改善功率晶体管的导通电阻和对应的硅面积。 功率晶体管可以包括漏极，源极和它们之间的沟道，被分成多个晶体管条，多个晶体管条被分组成多个不同的组。 功率晶体管还可以包括与漏极和源极之一相关联的第一顶部金属和与漏极和源极中的另一个相关联的第二顶部金属。 第二顶部金属包括耦合到不同组的晶体管条纹的至少一​​个部分。 还公开了用于确定功率晶体管的布局拓扑的相关方法。

公开(公告)号：US08159448B2

公开(公告)日：2012-04-17

申请号：US12317108

申请日：2008-12-19

申请人： Jeffrey G. Barrow

发明人： Jeffrey G. Barrow

IPC分类号： G09G3/36

CPC分类号： G05F3/16

摘要： Temperature-compensation network embodiments are provided to generate compensation signals which may be useful in improving the performance of a variety of important systems. An embodiment includes a limit current mirror configured to provide a limit current, a current generator to provide a slope current whose magnitude varies with temperature, and an output current mirror positioned to receive the limit current and the slope current and configured to provide a compensation current. In addition, a floating voltage reference is provided for use in various networks which include the temperature-compensation networks. The temperature-compensation networks may be used to improve performance in systems such as a panel driver which provides turn-on and turn-off gate voltages to transistors in liquid crystal displays.

摘要翻译： 提供温度补偿网络实施例以产生可用于改善各种重要系统的性能的补偿信号。 一个实施例包括配置成提供限制电流的限流电流镜，电流发生器以提供其幅度随温度变化的斜率电流，以及定位成接收限制电流和斜率电流并被配置为提供补偿电流的输出电流镜 。 另外，提供浮动电压基准用于包括温度补偿网络的各种网络中。 温度补偿网络可以用于提高系统中的性能，例如面板驱动器，其提供液晶显示器中的晶体管的导通和截止栅极电压。

公开(公告)号：US08004339B2

公开(公告)日：2011-08-23

申请号：US12622266

申请日：2009-11-19

申请人： Jeffrey G. Barrow

发明人： Jeffrey G. Barrow

IPC分类号： H03L5/00

CPC分类号： H03K19/0008 ,  H03K19/018521

摘要： A level-shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull-up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The output circuit may also include a pull-down circuit configured for pulling down the voltage on the output signal to a low voltage in responsive to a low-side control signal. The level-shifting circuit can also include a high-side inverting buffer operably coupled between an edge-controlled signal and the high-side control signal, and a low-side buffer configured for driving the low-side control signal responsive to an input signal. The level-shifting circuit may also include an edge-control buffer operably coupled between the input signal and the high-side inverting buffer and configured to generate the edge-controlled signal with a slow rise time relative to a fall time.

摘要翻译： 具有降低的直通电流的电平移动电路包括输出电路，其包括具有上拉电路的高电压装置，该上拉电路被配置为响应于高侧控制信号将输出信号上的电压提升到高电压。 输出电路还可以包括下拉电路，其被配置为响应于低侧控制信号而将输出信号上的电压降低到低电压。 电平移位电路还可以包括可操作地耦合在边缘控制信号和高侧控制信号之间的高侧反相缓冲器，以及响应于输入信号而驱动低侧控制信号的低侧缓冲器 。 电平移位电路还可以包括边缘控制缓冲器，其可操作地耦合在输入信号和高侧反相缓冲器之间，并被配置为相对于下降时间产生具有缓慢上升时间的边沿控制信号。

公开(公告)号：US07847634B2

公开(公告)日：2010-12-07

申请号：US12321708

申请日：2009-01-22

申请人： Jeffrey G. Barrow ,  A. Paul Brokaw

发明人： Jeffrey G. Barrow ,  A. Paul Brokaw

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F3/347

摘要： Error amplifier structures are provided to generate an error signal in response to the difference between an input signal (e.g., a feedback current) and a reference signal (e.g., a bias current). Amplifier embodiments generally include a reference generator and a differencing amplifier. In at least one embodiment, the error generator is arranged to generate first and second bias voltages that correspond to the bias current. In at least one embodiment, the differencing amplifier is configured to provide a reference current to an output node in response to the first bias voltage, provide a feedback current to the output node in response to the second bias voltage, and generate an error current in response to a voltage at the output node. The error amplifier structures are suited for use in various systems such as negative switching regulators.

摘要翻译： 提供误差放大器结构以响应于输入信号（例如，反馈电流）和参考信号（例如，偏置电流）之间的差异来产生误差信号。 放大器实施例通常包括参考发生器和差分放大器。 在至少一个实施例中，误差发生器被布置成产生对应于偏置电流的第一和第二偏置电压。 在至少一个实施例中，差分放大器被配置为响应于第一偏置电压向输出节点提供参考电流，响应于第二偏置电压向输出节点提供反馈电流，并且产生误差电流 响应于输出节点处的电压。 误差放大器结构适用于各种系统，如负开关稳压器。

公开(公告)号：US20080237630A1

公开(公告)日：2008-10-02

申请号：US12079841

申请日：2008-03-27

申请人： Jeffrey G. Barrow ,  Javier A. Salcedo ,  A. Paul Brokaw

发明人： Jeffrey G. Barrow ,  Javier A. Salcedo ,  A. Paul Brokaw

IPC分类号： H01L29/745

CPC分类号： H01L29/745 ,  H01L29/7408 ,  H01L29/7455

摘要： A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

摘要翻译： 半导体开关包括被布置为提供类SCR功能的PNPN结构，以及优选地集成在公共基板上的MOS栅极结构。 该开关包括用于MOS栅极的欧姆接触，以及用于PNPN结构的阴极和栅极区域; 阳极接触是固有的。 固定电压通常被施加到外部节点。 MOS栅极结构允许在导通时在外部节点和本征阳极之间传导电流，并且当适当的电压施加到栅极触点时，PNPN结构将电流从阳极传导到阴极。 再生反馈一旦开始进行就保持开关状态。 MOS门禁止外部节点和阳极之间的电流流动，从而在关闭时关闭开关。 当导通时，MOS栅极的沟道电阻用作镇流电阻。

公开(公告)号：US20120235846A1

公开(公告)日：2012-09-20

申请号：US13049728

申请日：2011-03-16

申请人： Lijie Zhao ,  Song Gao ,  Quinghua Hubert Yue ,  Jeffrey G. Barrow

发明人： Lijie Zhao ,  Song Gao ,  Quinghua Hubert Yue ,  Jeffrey G. Barrow

IPC分类号： H03M1/34

CPC分类号： H03M1/06 ,  H03M1/468

摘要： Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter.

摘要翻译： 逐次近似公开了模数转换器（ADC）及相关方法。 逐次逼近ADC包括具有比较器输出的比较器和耦合到公共模型信号和比较输入的输入。 控制逻辑产生响应于比较器输出的一个或多个控制信号。 电容器阵列包括可操作地耦合到阵列输出的电容器的第一侧。 电容器阵列响应于一个或多个控制信号选择性地将电容器的第二侧的每一个耦合到模拟输入信号和一个或多个输入参考信号。 电压限制器可操作地耦合在阵列输出和比较器的比较输入之间，并将比较输入端的电压限制在相对于阵列输出的预定范围内。 逐次逼近ADC也可以与第二比较器和第二限压器差分地配置。

公开(公告)号：US20120223647A1

公开(公告)日：2012-09-06

申请号：US13040077

申请日：2011-03-03

申请人： A. Paul Brokaw ,  June Her ,  Jeffrey G. Barrow

发明人： A. Paul Brokaw ,  June Her ,  Jeffrey G. Barrow

IPC分类号： H05B37/00

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2330/024 ,  G09G2330/028

摘要： Energy sharing circuits and related methods are disclosed herein. A high voltage can be selectively coupled to a first source line and a low voltage can be selectively coupled to a second source line during a first time period. During a subsequent time period, a first coupling switch is activated to inductively couple the first source line to the second source line and diode block the second source line from the first source line. During a subsequent time period, the low voltage is selectively coupled to the first source line and the high voltage is selectively coupled to the second source line. During a subsequent time period, a second coupling switch is activated to inductively couple the second source line to the first source line and diode block the first source line from the second source line.

摘要翻译： 本文公开了能量共享电路和相关方法。 高电压可以选择性地耦合到第一源极线，并且低电压可以在第一时间周期期间选择性地耦合到第二源极线。 在随后的时间段期间，激活第一耦合开关以将第一源极线耦合到第二源极线，并且将第二源极线与第一源极线截取二极管。 在随后的时间段期间，低电压选择性地耦合到第一源极线，并且高电压选择性地耦合到第二源极线。 在随后的时间段期间，激活第二耦合开关以将第二源极线耦合到第一源极线，并且将第二源极线与第二源极线截获。

公开(公告)号：US08085180B2

公开(公告)日：2011-12-27

申请号：US12714042

申请日：2010-02-26

申请人： Jeffrey G. Barrow ,  Benjamin O. Barrow

发明人： Jeffrey G. Barrow ,  Benjamin O. Barrow

IPC分类号： H03M1/34

CPC分类号： H03M1/0646 ,  H03M1/365

摘要： An analog-to-digital converter with comparators with multiple, inter-coupled, outputs is provided, which may be also called a Benorion Analog-to-Digital Converter (ADC) or a Benorion Converter. The analog-to-digital converter includes a plurality of comparators operably coupled for receiving an analog input signal and configured for comparing the analog input signal with a plurality of voltage reference signals. Each comparator of the plurality is configured for generating a plurality of comparator outputs comprising a primary comparator output, and at least one additional comparator output selected from the group consisting of positive comparator outputs and negative comparator. The analog-to-digital converter further includes a plurality of composite outputs, each composite output of the plurality comprising a combination of the primary comparator output from a corresponding comparator of the plurality and at least one additional comparator output from at least one additional comparator of the plurality of comparators. Other comparators and methods are provided.

摘要翻译： 提供了具有多个互耦合输出的比较器的模数转换器，其也可称为Benorion模数转换器（ADC）或Benorion转换器。 该模数转换器包括多个比较器，其可操作地耦合用于接收模拟输入信号并且被配置为将模拟输入信号与多个电压参考信号进行比较。 多个的每个比较器被配置用于产生包括主比较器输出的多个比较器输出，以及从由正比较器输出和负比较器组成的组中选择的至少一个附加比较器输出。 模数转换器还包括多个复合输出，多个复合输出包括来自多个对应比较器的主比较器输出和至少一个附加比较器输出的组合，至少一个附加比较器输出来自至少一个附加比较器 多个比较器。 提供了其他比较和方法。