公开(公告)号：US20090087978A1

公开(公告)日：2009-04-02

申请号：US11958974

申请日：2007-12-18

申请人： Chao-Wen Lay ,  Jen-Jui Huang

发明人： Chao-Wen Lay ,  Jen-Jui Huang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76831

摘要： An interconnect process is provided. A substrate is provided. A plurality of gate structures is disposed on the substrate, and doped regions are disposed in the substrate and respectively located between two adjacent gate structure. A liner is conformally formed above the substrate. A dielectric layer is formed above the substrate. A contact opening is formed in the dielectric layer between two neighboring gate structures to expose the liner on the doped region and on a portion of the top surface and a portion of the sidewall of each of the gate structures. A polymer material is deposited on the liner on the portion of the top surface of each of the gate structures and on the doped region. The liner on the doped regions is removed. A conductive layer is filled in the contact opening, which is free of electrical connection to the gate structures.

摘要翻译： 提供互连过程。 提供基板。 多个栅极结构设置在衬底上，并且掺杂区域设置在衬底中并分别位于两个相邻栅极结构之间。 衬垫保形地形成在衬底之上。 在衬底上形成介电层。 在两个相邻栅极结构之间的电介质层中形成接触开口以暴露掺杂区域上的衬垫以及每个栅极结构的顶表面的一部分和侧壁的一部分。 聚合物材料沉积在每个栅极结构的顶表面的部分上和衬底上的掺杂区上。 去除掺杂区域上的衬垫。 导电层填充在接触开口中，该接触开口不与门结构电连接。

公开(公告)号：US20050275046A1

公开(公告)日：2005-12-15

申请号：US10865763

申请日：2004-06-14

申请人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

发明人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L31/062

CPC分类号： H01L21/28044

摘要： A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.

摘要翻译： 通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中， 过渡金属是钛，钽或钴。 对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。 界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。 封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。 在将多晶硅层图案化之前打开氮化物衬垫。 作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。 提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。

公开(公告)号：US08658051B2

公开(公告)日：2014-02-25

申请号：US12119275

申请日：2008-05-12

申请人： Kuo-Yao Cho ,  Wen-Bin Wu ,  Ya-Chih Wang ,  Chiang-Lin Shih ,  Chao-Wen Lay ,  Chih-Huang Wu

发明人： Kuo-Yao Cho ,  Wen-Bin Wu ,  Ya-Chih Wang ,  Chiang-Lin Shih ,  Chao-Wen Lay ,  Chih-Huang Wu

IPC分类号： C23F1/00 ,  B44C1/22 ,  H01L21/306

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.

摘要翻译： 一种改善半导体上的光刻分辨率的方法，包括提供其上依次形成保护层，第一蚀刻层和光致抗蚀剂层的基板的步骤; 图案化光致抗蚀剂层以形成开口，以便部分地露出第一蚀刻层; 将第一离子注入到所揭示的第一蚀刻层中以形成第一掺杂区域; 以及将第二离子注入到所揭示的第一蚀刻层中以形成第二掺杂区域，其中所述第一掺杂区域与所述第二掺杂区域无关。

公开(公告)号：US08222163B2

公开(公告)日：2012-07-17

申请号：US12851561

申请日：2010-08-06

申请人： Chao-Wen Lay ,  Ching-Kai Lin

发明人： Chao-Wen Lay ,  Ching-Kai Lin

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/302 ,  H01L21/02238 ,  H01L21/30604

摘要： A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.

摘要翻译： 由于干蚀刻，凹槽通常形成在沟槽的侧壁上。 凹槽可影响形成在沟槽中的元件的轮廓。 因此，提供了在基板中使凹部变平的方法。 该方法包括：首先，提供其中具有沟槽的衬底，其中沟槽具有包括凹陷部分和未加工部分的侧壁。 然后，进行凹部氧化速度变化步骤，以改变凹部的氧化速率。 然后，对基板进行氧化处理，以在凹部上形成第一氧化物层，在未加工部分上形成第二氧化物层，其中第二氧化物层比第一氧化物层厚。 最后，去除第一氧化物层和第二氧化物层以形成沟槽的扁平侧壁。

公开(公告)号：US20120034791A1

公开(公告)日：2012-02-09

申请号：US12851561

申请日：2010-08-06

申请人： Chao-Wen Lay ,  Ching-Kai Lin

发明人： Chao-Wen Lay ,  Ching-Kai Lin

IPC分类号： H01L21/316

CPC分类号： H01L21/302 ,  H01L21/02238 ,  H01L21/30604

摘要： A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.

摘要翻译： 由于干蚀刻，凹槽通常形成在沟槽的侧壁上。 凹槽可影响形成在沟槽中的元件的轮廓。 因此，提供了在基板中使凹部变平的方法。 该方法包括：首先，提供其中具有沟槽的衬底，其中沟槽具有包括凹陷部分和未加工部分的侧壁。 然后，进行凹部氧化速度变化步骤，以改变凹部的氧化速率。 然后，对基板进行氧化处理，以在凹部上形成第一氧化物层，在未加工部分上形成第二氧化物层，其中第二氧化物层比第一氧化物层厚。 最后，去除第一氧化物层和第二氧化物层以形成沟槽的扁平侧壁。

公开(公告)号：US07078748B2

公开(公告)日：2006-07-18

申请号：US10865763

申请日：2004-06-14

申请人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

发明人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

IPC分类号： H01L27/148

CPC分类号： H01L21/28044

摘要： A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.

摘要翻译： 通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中， 过渡金属是钛，钽或钴。 对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。 界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。 封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。 在将多晶硅层图案化之前打开氮化物衬垫。 作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。 提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。

公开(公告)号：US06759300B2

公开(公告)日：2004-07-06

申请号：US10424526

申请日：2003-04-28

申请人： Chao-Wen Lay ,  Yu-Chi Sun ,  Tse-Yao Huang

发明人： Chao-Wen Lay ,  Yu-Chi Sun ,  Tse-Yao Huang

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/42324

摘要： A method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conductive layer, a first insulating layer, and a patterned mask layer with an opening are formed, such that the opening exposes the first insulating layer. The insulating layer and the conducting layer are sequentially etched to form a round-cornered trench, and the photo hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are removed using the second insulating layer as a mask, and the first conducting layer covered by the second insulating layer remains as a floating gate.

摘要翻译： 一种用于制造浮动栅极的方法。 提供半导体衬底，其上形成有栅极电介质层，导电层，第一绝缘层和具有开口的图案化掩模层，使得开口暴露第一绝缘层。 依次蚀刻绝缘层和导电层以形成圆角沟槽，并去除光硬掩模层。 在圆角沟槽中形成第二绝缘层。 使用第二绝缘层作为掩模去除第一绝缘层和暴露的导电层，并且由第二绝缘层覆盖的第一导电层保持为浮栅。