公开(公告)号：US5479119A

公开(公告)日：1995-12-26

申请号：US344452

申请日：1994-11-23

Applicant: Thomas E. Tice ,  David T. Crook ,  Kevin M. Kattmann ,  Charles D. Lane

Inventor： Thomas E. Tice ,  David T. Crook ,  Kevin M. Kattmann ,  Charles D. Lane

IPC: G01R19/00 ,  G01R19/165 ,  H02H7/20 ,  H03F1/52 ,  H03G11/00 ,  H03M1/12 ,  H03K5/153

CPC classification number: H03G11/00 ,  H03F1/52

Abstract: An overvoltage protection circuit protects against saturation and damage of sensitive circuitry elements. The protection circuit includes an out-of-range detector which compares an input signal to reference levels to determine if it is within a predetermined range of acceptable inputs. If the input is determined not to be within this range, a control circuit substitutes a supplemental signal within the range for the input signal. Digital correction can be provided to correct the output of the sensitive circuit element while the supplemental signal is being substituted. Numerous circuit designs may be used to implement the protection scheme.

Abstract translation: 过压保护电路可以防止敏感电路元件的饱和和损坏。 保护电路包括超出范围检测器，其将输入信号与参考电平进行比较，以确定其是否在可接受输入的预定范围内。 如果确定输入不在该范围内，则控制电路将输入信号范围内的补充信号代入。 可以提供数字校正以在补充信号被替代时校正敏感电路元件的输出。 可以使用许多电路设计来实现保护方案。

公开(公告)号：US4928103A

公开(公告)日：1990-05-22

申请号：US408278

申请日：1989-09-18

Applicant: Charles D. Lane

Inventor： Charles D. Lane

IPC: H03M1/20 ,  H03M1/36

CPC classification number: H03M1/206 ,  H03M1/361

Abstract: The invention comprises an n-bit analog-to-digital flash converter comprising 2.sup.n /2 input comparators, each having a first input coupled to receive the analog voltage to be converted and a second input coupled to a different reference voltage. The reference voltages of each consecutive input comparator are spaced apart two LSBs of the converter. Each input comparator has two output, OUT and an inverted version thereof, OUT. 2.sup.n -1 consecutive latches are provided. Every other latch receives at its inputs the OUT and OUT signals from a single associated input comparator. All other latches receive the OUT signal of one of the input comparators and the OUT signal of an adjacent input comparator. The latches having inputs coupled to the OUT and OUT signals of a single input comparator produce a comparison output which change state every two LSBs of the converter and the latches having one input coupled to the OUT signal of one input comparator and the OUT signal of an adjacent input comparator produce comparison signals which change state halfway between the output signals of the adjacent latches. Thus, a comparison output is provided for every LSB of the full scale range of the converter using only 2.sup.n /2 input comparators.

Abstract translation: 本发明包括一个包括2n / 2个输入比较器的n位模数转换闪存转换器，每个具有耦合以接收要转换的模拟电压的第一输入和耦合到不同参考电压的第二输入。 每个连续输入比较器的参考电压间隔开转换器的两个LSB。 每个输入比较器有两个输出OUT和它们的反向版本，并且提供了2n-1个连续的锁存器。 每个其他锁存器在其输入端接收来自单个相关输入比较器的OUT和＆amp; upbar＆O信号。 所有其他锁存器都接收输入比较器之一的OUT信号和相邻输入比较器的＆upbar＆O信号。 具有耦合到单个输入比较器的OUT和＆amp; upbar＆O信号的输入的锁存器产生比较输出，其改变转换器的每两个LSB的状态，并且具有耦合到一个输入比较器的OUT信号的一个输入的锁存器和＆amp; 相邻输入比较器产生比较信号，其改变相邻锁存器的输出信号之间的状态。 因此，仅使用2n / 2输入比较器，为转换器满量程范围的每个LSB提供比较输出。

公开(公告)号：US06480136B1

公开(公告)日：2002-11-12

申请号：US09851658

申请日：2001-05-08

Applicant: Rodney Louis Kranz ,  Charles D. Lane ,  David Jarman

Inventor： Rodney Louis Kranz ,  Charles D. Lane ,  David Jarman

IPC: H03M106

CPC classification number: H03M1/0678 ,  H03M1/36

Abstract: An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply and producing a corresponding output signal; the improvement for reducing the effects of cell mismatch and output circuit mismatch including an impedance network, having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuit devices with each circuit device forming a part of a respective output circuit, the impedance elements reducing the effects of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatches in both the cells and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.

Abstract translation: 一种集成电路，包括响应于各个输入产生输出信号的多个重复单元，每个单元具有与其相关联的输出电路，响应于单元输出信号以产生输出电路输出信号，每个输出电路包括电路 具有两个端子以提供来自相关电流源的电流的流动并产生相应的输出信号; 用于减少电池失配和输出电路失配的影响的改进，包括阻抗网络，其具有各自连接在相应端子或相应电路装置对之间的一组阻抗元件，每个电路装置形成相应输出电路的一部分， 阻抗元件减少电池失配和输出电路失配对输出信号的影响; 可能存在一个阻抗网络，其适应电池和输出电路中的不匹配，或者可以存在一个阻抗网络以适应电池失配，另一个阻抗网络适应输出电路不匹配。

公开(公告)号：US5706008A

公开(公告)日：1998-01-06

申请号：US609651

申请日：1996-03-01

Applicant: Roger B. Huntley, Jr. ,  Thomas E. Tice ,  Charles D. Lane

Inventor： Roger B. Huntley, Jr. ,  Thomas E. Tice ,  Charles D. Lane

IPC: H03M1/06 ,  H03M1/36

CPC classification number: H03M1/0682 ,  H03M1/363

Abstract: A new differential ladder/comparator circuit reduces settling time delays in parallel analog to digital converters. A parallel analog-to-digital converter (ADC) includes a pair of differential resistor ladders having their taps connected to a group of comparators. The comparators produce digital "thermometer" scale outputs corresponding to analog signals impressed upon the differential ladders. By employing double-value resistors to form the "rungs" of the ladders and by connecting the comparators to the ladder taps in a way that increases the number of comparator inputs connected to the ladders' lower-order taps and decreases the number of comparator inputs connected to the ladders' higher order taps, the input impedance presented by the ladder/comparator combination is reduced in comparison with conventional differential ladder parallel ADCs. Additionally, input signals are superimposed upon the ladders by drivers which, in a preferred embodiment, present lower output impedances to the ladders than prior art drivers, further improving the bandwidth of the ADC.

Abstract translation: 新的差分梯形图/比较器电路减少并行模数转换器的稳定时间延迟。 并行模数转换器（ADC）包括一对具有连接到一组比较器的抽头的差分电阻梯。 比较器产生对应于印在差分梯子上的模拟信号的数字“温度计”刻度输出。 通过采用双值电阻器来形成梯子的“梯级”，并通过将比较器连接到梯形抽头，以增加连接到梯级低阶抽头的比较器输入的数量并减少比较器输入的数量 连接到梯子的高阶抽头，与传统的差分梯形并行ADC相比，梯形图/比较器组合所呈现的输入阻抗减小。 此外，输入信号通过驱动器叠加在梯子上，在优选实施例中，驱动器向梯子提供比现有技术驱动器更低的输出阻抗，进一步提高了ADC的带宽。

公开(公告)号：US5757234A

公开(公告)日：1998-05-26

申请号：US642388

申请日：1996-05-03

Applicant: Charles D. Lane

Inventor： Charles D. Lane

IPC: H03F3/26 ,  H03F3/45 ,  H03M1/12

CPC classification number: H03F3/45479 ,  H03F3/26

Abstract: A residue amplifier includes input and output differential amplifiers. The output differential amplifier includes temperature-dependent current sources which compensate for temperature dependent gain variations within the input differential amplifier. Amplifier components are chosen to produce an overall gain equal to a ratio of fixed resistors, at a nominal temperature. The compensating current sources maintain this fixed gain value as the amplifier's operating temperature varies.

Abstract translation: 残留放大器包括输入和输出差分放大器。 输出差分放大器包括依赖于温度的电流源，用于补偿输入差分放大器内与温度有关的增益变化。 选择放大器组件以在标称温度下产生等于固定电阻器的比率的总增益。 当放大器的工作温度变化时，补偿电流源保持该固定增益值。

公开(公告)号：US5661422A

公开(公告)日：1997-08-26

申请号：US571243

申请日：1995-12-12

Applicant: Thomas E. Tice ,  David T. Crook ,  Kevin M. Kattmann ,  Charles D. Lane

Inventor： Thomas E. Tice ,  David T. Crook ,  Kevin M. Kattmann ,  Charles D. Lane

IPC: H03M1/12 ,  H03M1/14 ,  H03K5/153

CPC classification number: H03M1/129 ,  H03M1/145

Abstract: A protection circuit inhibits saturation and damage of sensitive circuit elements when an input signal goes out of a nominal input range. The protection circuit includes an out-of-range detector which compares the input signal to reference levels to determine if it is within the range. If it is not, a control circuit substitutes a supplemental signal that is slightly out of range, but not so far out of range as to cause any substantial saturation. Supplemental signal sources that produce supplemental signals slightly outside the high and low ends of the range with error margins, not more than about 750 mV, that lie just outside the range; an out-of-range input is replaced by the supplemental signal with the closest value. The invention is particularly applicable to multistep/subranging analog-to-digital/converters.

Abstract translation: 当输入信号超出标称输入范围时，保护电路可以抑制敏感电路元件的饱和和损坏。 保护电路包括超出范围的检测器，其将输入信号与参考电平进行比较，以确定其是否在该范围内。 如果不是这样，则控制电路将稍微超出范围的补充信号代替，但是不能超出范围，导致任何显着的饱和。 补充信号源产生稍微超出范围的高端和低端的补充信号，误差范围不大于约750mV，处于范围之外; 超范围输入由具有最接近的值的补充信号代替。 本发明特别适用于模数转换器的多级/次级化。

公开(公告)号：US5530444A

公开(公告)日：1996-06-25

申请号：US368862

申请日：1995-01-05

Applicant: Thomas E. Tice ,  David T. Crook ,  Kevin M. Kattmann ,  Charles D. Lane

Inventor： Thomas E. Tice ,  David T. Crook ,  Kevin M. Kattmann ,  Charles D. Lane

IPC: H03F1/08 ,  H03F3/45 ,  H03M1/16 ,  H03M1/14

CPC classification number: H03F3/45098 ,  H03F1/083 ,  H03F3/45085 ,  H03F2203/45392 ,  H03F2203/45702 ,  H03F2203/45722 ,  H03F2203/5003 ,  H03M1/16

Abstract: Open-loop differential amplifiers (120, 140) are disclosed which have accurate and stable gain. The gain of these amplifiers is substantially insensitive to the effects of small-signal emitter resistance r.sub.e, current gain .beta. and Early voltage V.sub.A. Thus, their gain can be accurately set by resistance ratios which makes them particularly useful in integrated circuits. These advantages are obtained with an output differential pair (67) that has cross-coupled base and collector terminals. In addition, resistors (141, 143, 148, 150) and a current source (146) associated with this differential pair are related to like elements (27, 28, 24, 25 and 26) that are associated with an input differential pair (21) by disclosed numerical ratios, e.g., the nominal gain G of the amplifier. Versions of the amplifiers can be adapted for use as a residue amplifier (162) in a subranging A/D converter (160).

Abstract translation: 公开了具有准确和稳定增益的开环差分放大器（120,140）。 这些放大器的增益对小信号发射极电阻re，电流增益β和早期电压VA的影响基本上不敏感。 因此，它们的增益可以通过电阻比来精确地设定，这使得它们在集成电路中特别有用。 这些优点通过具有交叉耦合基极和集电极端子的输出差分对（67）获得。 另外，与该差分对相关联的电阻（141,143,148,150）和电流源（146）与与输入差分对相关联的相似元件（27,28,24,25和26）有关 21）通过公开的数值比例，例如放大器的标称增益G。 放大器的版本可以适用于在亚排A / D转换器（160）中的残留放大器（162）。