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    OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
    4.
    发明申请
    OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE 有权
    通过掩蔽和反应离子蚀刻（RIE）技术的超耐性

    公开(公告)号：US20140061930A1

    公开(公告)日：2014-03-06

    申请号：US13604660

    申请日：2012-09-06

    申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

    摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

    Electrical fuse structure and method of fabricating same
    5.
    发明授权
    Electrical fuse structure and method of fabricating same 有权
    电熔丝结构及其制造方法

    公开(公告)号：US08609534B2

    公开(公告)日：2013-12-17

    申请号：US12890941

    申请日：2010-09-27

    申请人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

    发明人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5256 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.

    摘要翻译： 使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。 双镶嵌结构包括图案化电介质材料，其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。 通孔开口位于顶部并连接到金属层。 双镶嵌结构还包括线路开口和通孔开口内的导电特征。 电介质间隔物也存在于线路开口和通孔开口内。 介电间隔物存在于图案化电介质材料的垂直侧壁上，并将导电特征与图案化电介质材料分开。 在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。 因此，提供了节省空间的高编程效率电熔丝。

    DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME
    6.
    发明申请
    DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME 有权
    双重对等双向对联方案

    公开(公告)号：US20130328208A1

    公开(公告)日：2013-12-12

    申请号：US13490542

    申请日：2012-06-07

    申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/28

    CPC分类号： H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

    摘要翻译： 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

    Metal Alloy Cap Integration
    7.
    发明申请
    Metal Alloy Cap Integration 审中-公开
    金属合金盖整合

    公开(公告)号：US20130112462A1

    公开(公告)日：2013-05-09

    申请号：US13290557

    申请日：2011-11-07

    申请人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

    发明人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

    IPC分类号： H05K1/09 ,  H05K3/00

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T29/49124 ,  H01L2924/00

    摘要： A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer.

    摘要翻译： 包括金属合金覆盖层的金属互连结构及其制造方法。 互连特征内的原始沉积的合金覆盖层元件将扩散到并分离到金属互连的顶表面上。 金属合金覆盖材料沉积在回流铜表面上，并且不物理地与互连特征的侧壁接触。 因此，互连结构中的残余合金元素的电阻率冲击降低。 也就是说，在金属互连结构的特征内部存在合金元素的减少。 金属互连结构包括具有凹陷线的介电层，侧壁上的衬垫材料，铜材料，合金盖和覆盖层。

    LOW-PROFILE LOCAL INTERCONNECT AND METHOD OF MAKING THE SAME
    9.
    发明申请
    LOW-PROFILE LOCAL INTERCONNECT AND METHOD OF MAKING THE SAME 有权
    低剖面局部互连及其制作方法

    公开(公告)号：US20120326237A1

    公开(公告)日：2012-12-27

    申请号：US13169081

    申请日：2011-06-27

    申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    IPC分类号： H01L29/772

    CPC分类号： H01L21/76895 ,  H01L21/823475 ,  H04L45/58 ,  H04L49/15 ,  H04L49/45

    摘要： Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.

    摘要翻译： 本发明的实施例提供一种结构。 该结构包括多个场效应晶体管，其具有形成在半导体衬底顶部上的栅极叠层，该栅叠层具有形成在其侧壁上的隔离层; 以及直接形成在半导体衬底的顶部上并将多个场效应晶体管之一的至少一个源极/漏极互连到多个场效应中的另一个的至少一个源极/漏极的一个或多个导电触点 晶体管，其中所述一个或多个导电触点是具有低于所述栅极堆叠的高度的高度的低轮廓局部互连的一部分。

    Method of forming borderless contact for transistor
    10.
    发明授权
    Method of forming borderless contact for transistor 失效
    形成晶体管无边界接触的方法

    公开(公告)号：US08232204B1

    公开(公告)日：2012-07-31

    申请号：US13171527

    申请日：2011-06-29

    申请人： David V. Horak ,  Charles W. Koburger, III ,  Steven J. Holmes ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： David V. Horak ,  Charles W. Koburger, III ,  Steven J. Holmes ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76834 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/78

    摘要： Embodiments of the present invention provide a method of forming borderless contact for transistor. The method may include forming a gate of a transistor, on top of a substrate, and spacers adjacent to sidewalls of the gate; forming a sacrificial layer surrounding the gate; causing the sacrificial layer to expand in height to become higher than the gate, the expanded sacrificial layer covering at most a portion of a top surface of the spacers and thereby leaving an opening on top of the gate surrounded by the spacers; filling the opening with a dielectric cap layer; replacing the expanded sacrificial layer with a dielectric layer; and forming a conductive stud contacting source/drain of the transistor, the conductive stud being isolated from the gate by the dielectric cap layer.

    摘要翻译： 本发明的实施例提供一种形成晶体管的无边界接触的方法。 该方法可以包括在衬底的顶部上形成晶体管的栅极和邻近栅极的侧壁的间隔物; 形成围绕所述栅极的牺牲层; 导致牺牲层在高度上膨胀以变得高于栅极，所述扩展的牺牲层覆盖所述间隔物的顶表面的至多一部分，从而在由所述间隔物包围的所述栅极的顶部上留下开口; 用介电盖层填充开口; 用介电层代替扩展的牺牲层; 并且形成与晶体管的导电柱接触的源极/漏极，导电柱通过电介质盖层与栅极隔离。