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    Method of selectively making copper using plating technology
    3.
    发明授权
    Method of selectively making copper using plating technology 有权
    使用电镀技术选择性制作铜的方法

    公开(公告)号：US06841466B1

    公开(公告)日：2005-01-11

    申请号：US10672395

    申请日：2003-09-26

    申请人： Chen-Hua Yu ,  Horng-Huei Tseng

    发明人： Chen-Hua Yu ,  Horng-Huei Tseng

    IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/7684 ,  H01L21/76879

    摘要： A method of forming a more uniform copper interconnect layer is described. A dielectric layer, electroconductive (EC) layer, and a photoresist layer are sequentially deposited on a substrate. An opening in the photoresist is etched through the dielectric layer while the EC layer serves as a hard mask. Following deposition of a diffusion barrier layer and copper seed layer on the EC layer and in the opening, the copper seed layer is removed above the EC layer by a first CMP step. The EC layer serves as a CMP stop to protect the dielectric layer and provides a more uniform surface for subsequent steps. Copper is selectively deposited on the seed layer within the opening. A second CMP step lowers the copper layer to be coplanar with the dielectric layer and removes the EC layer. The resulting copper interconnect layer has a more uniform thickness and surface for improved performance.

    摘要翻译： 描述形成更均匀的铜互连层的方法。 电介质层，导电（EC）层和光致抗蚀剂层顺序沉积在基片上。 通过介电层蚀刻光致抗蚀剂中的开口，而EC层用作硬掩模。 在EC层和开口中沉积扩散阻挡层和铜籽晶层之后，通过第一CMP步骤在EC层上方去除铜籽晶层。 EC层用作CMP阻挡层，以保护电介质层，并为后续步骤提供更均匀的表面。 铜选择性地沉积在开口内的种子层上。 第二CMP步骤降低铜层与电介质层共面并去除EC层。 所得的铜互连层具有更均匀的厚度和表面以提高性能。

    Interconnect with composite barrier layers and method for fabricating the same
    5.
    发明授权
    Interconnect with composite barrier layers and method for fabricating the same 有权
    与复合阻挡层互连及其制造方法

    公开(公告)号：US06958291B2

    公开(公告)日：2005-10-25

    申请号：US10654757

    申请日：2003-09-04

    申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

    发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76846

    摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.

    摘要翻译： 复合ALD形成的扩散阻挡层。 在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。 优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

    Copper wiring with high temperature superconductor (HTS) layer
    6.
    发明申请
    Copper wiring with high temperature superconductor (HTS) layer 有权
    铜线与高温超导体（HTS）层

    公开(公告)号：US20050077627A1

    公开(公告)日：2005-04-14

    申请号：US10684224

    申请日：2003-10-10

    申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Chenming Hu ,  Chao-Hsiung Wang

    发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Chenming Hu ,  Chao-Hsiung Wang

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L23/48

    CPC分类号： H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer includes a superconductor material comprised of barium copper oxide and a rare earth element. The rare earth element yttrium is particularly suitable. For semiconductor devices having other semiconductor circuits or elements above the wiring, a capping layer of HTS material is deposited over the wiring before a cover layer of dielectric is deposited.

    摘要翻译： 使用HTS（高温超导体）层与介电材料和铜（或其它金属）导电布线之间的典型扩散层组合形成半导体器件的半导体器件和方法。 HTS层包括由氧化钡钡和稀土元素构成的超导体材料。 稀土元素钇特别适合。 对于具有其它半导体电路或布线之上的元件的半导体器件，在沉积覆盖层的电介质之前，在布线上沉积HTS材料的覆盖层。

    Via recess in underlying conductive line
    7.
    发明授权
    Via recess in underlying conductive line 有权
    通过下面的导电线路中的凹槽

    公开(公告)号：US07180193B2

    公开(公告)日：2007-02-20

    申请号：US10823159

    申请日：2004-04-13

    申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    IPC分类号： H01L23/522

    CPC分类号： H01L23/5329 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The conductive line is underlying the dielectric layer. The via is formed in the dielectric layer and extends into the conductive line to form the via recess in the conductive line. The via recess formed in the conductive line has a depth of at least about 100 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.

    摘要翻译： 半导体器件包括导电线中的电介质层，导电线，通孔和通路凹槽。 导电线在电介质层的下面。 通孔形成在电介质层中并延伸到导电线中以在导电线中形成通路凹槽。 形成在导电线中的通路凹槽具有至少约100埃的深度。 通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。 例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。 例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。

    Via recess in underlying conductive line
    8.
    发明申请
    Via recess in underlying conductive line 有权
    通过下面的导电线路中的凹槽

    公开(公告)号：US20050224855A1

    公开(公告)日：2005-10-13

    申请号：US10823159

    申请日：2004-04-13

    申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    IPC分类号： G03G15/16 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L23/5329 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The conductive line is underlying the dielectric layer. The via is formed in the dielectric layer and extends into the conductive line to form the via recess in the conductive line. The via recess formed in the conductive line has a depth of at least about 100 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.

    摘要翻译： 半导体器件包括导电线中的电介质层，导电线，通孔和通路凹槽。 导电线在电介质层的下面。 通孔形成在电介质层中并延伸到导电线中以在导电线中形成通路凹槽。 形成在导电线中的通路凹槽具有至少约100埃的深度。 通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。 例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。 例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。

    Tungsten-copper interconnect and method for fabricating the same
    9.
    发明申请
    Tungsten-copper interconnect and method for fabricating the same 审中-公开
    钨铜互连及其制造方法

    公开(公告)号：US20050064629A1

    公开(公告)日：2005-03-24

    申请号：US10665309

    申请日：2003-09-22

    申请人： Chen-Hua Yu ,  Tsu Shih ,  Chung-Shi Liu ,  Shwang-Min Jeng ,  Horng-Huei Tseng

    发明人： Chen-Hua Yu ,  Tsu Shih ,  Chung-Shi Liu ,  Shwang-Min Jeng ,  Horng-Huei Tseng

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76829 ,  H01L21/76834

    摘要： An interconnect structure utilizing a silicon carbon-containing film as an interlayer between dielectrics. A semiconductor substrate having a conductor thereon is provided, and an insulating layer overlies the semiconductor substrate. The insulating layer has a via hole therein to expose the conductor. A conductive plug, e.g. a tungsten plug, substantially fills the via hole and electrically connects the underlying conductor. A silicon carbon-containing film and a low k dielectric layer overlie the insulating layer and the conductive plug, and have a trench therein exposing the conductive plug. A copper or copper alloy conductor substantially fills the trench.

    摘要翻译： 利用含硅碳膜作为电介质之间的中间层的互连结构。 设置有其上具有导体的半导体衬底，并且绝缘层覆盖在半导体衬底上。 绝缘层在其中具有通孔以露出导体。 导电塞，例如。 钨插头基本上填充通孔并电连接下面的导体。 含硅碳膜和低k电介质层覆盖在绝缘层和导电插塞上，并且在其中具有暴露导电插塞的沟槽。 铜或铜合金导体基本上填充沟槽。

    Interconnect with composite layers and method for fabricating the same
    10.
    发明授权
    Interconnect with composite layers and method for fabricating the same 有权
    与复合层互连及其制造方法

    公开(公告)号：US07265447B2

    公开(公告)日：2007-09-04

    申请号：US11240216

    申请日：2005-09-30

    申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

    发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76846

    摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.

    摘要翻译： 复合ALD形成的扩散阻挡层。 在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。 优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。