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55 条记录 (耗时 0.037 秒)

    Semiconductor Structure and Manufacturing Method for the Same
    2.
    发明申请
    Semiconductor Structure and Manufacturing Method for the Same 有权
    半导体结构及其制造方法

    公开(公告)号：US20120280316A1

    公开(公告)日：2012-11-08

    申请号：US13101486

    申请日：2011-05-05

    申请人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    发明人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0684 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/861

    摘要： A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type.

    摘要翻译： 提供了一种半导体结构及其制造方法。 半导体结构包括第一掺杂阱，第一掺杂电极，第二掺杂电极，掺杂条和掺杂顶区。 掺杂条在第一掺杂电极和第二掺杂电极之间的第一掺杂阱上。 掺杂的条带彼此分离。 掺杂的顶部区域在掺杂的条带上并且在掺杂条带之间的第一掺杂阱上延伸。 第一掺杂阱和掺杂顶区具有第一导电类型。 掺杂的条带具有与第一导电类型相反的第二导电类型。

    Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same
    4.
    发明申请
    Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same 有权
    超高压N型金属氧化物半导体（UHV NMOS）器件及其制造方法

    公开(公告)号：US20120241861A1

    公开(公告)日：2012-09-27

    申请号：US13070819

    申请日：2011-03-24

    申请人： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    发明人： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66477 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.

    摘要翻译： 提供了具有改进性能的超高电压n型金属氧化物半导体（UHV NMOS）器件及其制造方法。 UHV NMOS包括P型材料的衬底; 设置在所述基板的一部分中的第一高压N阱（HVNW）区域; 与第一HVNW区域的一侧相邻的源极和体积p阱（PW），源极和体积PW包括源极和体积; 从源极和体积PW延伸到第一HVNW区域的一部分的栅极，以及设置在与栅极相对的第一HVNW区域的另一部分内的漏极; 设置在第一HVNW区域内的P顶层，位于漏极与源极和体PW之间的P顶层; 以及形成在P顶层上的n型注入层。

    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体结构及其制造方法

    公开(公告)号：US20130265102A1

    公开(公告)日：2013-10-10

    申请号：US13442340

    申请日：2012-04-09

    申请人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Ching-Lin Chan ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    发明人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Ching-Lin Chan ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    IPC分类号： H01L29/808 ,  G11C5/14 ,  H01L21/337

    CPC分类号： H01L29/66901 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/808

    摘要： A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type formed in the deep well and extending down from the surface of the substrate; and a second well having the second conductive type formed in the deep well and extending down from the surface of the substrate, and the second well adjacent to the first well. The first well includes a block region and plural finger regions joined to one side of the block region, while the second well includes plural channel regions interlaced with the finger regions to separate the finger regions.

    摘要翻译： 提供了半导体结构及其制造方法。 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 第一阱具有形成在深阱中并从衬底表面向下延伸的第一导电类型; 以及第二阱，其具有形成在深阱中并从衬底的表面向下延伸的第二导电类型，以及与第一阱相邻的第二阱。 第一阱包括连接到块区域的一侧的块区域和多个指状区域，而第二阱包括与手指区域交织的多个沟道区域以分离手指区域。