公开(公告)号：US20130010560A1

公开(公告)日：2013-01-10

申请号：US13535075

申请日：2012-06-27

Applicant: Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

Inventor： Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

IPC: H03F3/45 ,  G11C7/06

CPC classification number: G11C7/067 ,  G11C7/065

Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.

Abstract translation: 电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。 第一电流镜电路具有参考端和镜像端。 第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。 第二个当前次级电路具有参考端和镜像端。 第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

公开(公告)号：US20130003445A1

公开(公告)日：2013-01-03

申请号：US13609930

申请日：2012-09-11

Applicant: Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C11/40 ,  H01L21/8244

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line

Abstract translation: 静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。 第一晶体管耦合在第一节点和第一位线之间。 第二晶体管耦合在第二节点和第二位线之间。 第三晶体管与第一节点耦合。 第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。 第五晶体管耦合在第三晶体管和第三位线之间

公开(公告)号：US20120182792A1

公开(公告)日：2012-07-19

申请号：US13008992

申请日：2011-01-19

Applicant: Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Hsu-Shun CHEN ,  Chung-Ji LU ,  Cheng-Hung LEE ,  Hung-Jen LIAO

Inventor： Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Hsu-Shun CHEN ,  Chung-Ji LU ,  Cheng-Hung LEE ,  Hung-Jen LIAO

IPC: G11C11/413 ,  G11C5/14

CPC classification number: G11C11/413

Abstract: A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.

Abstract translation: SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

公开(公告)号：US20110063894A1

公开(公告)日：2011-03-17

申请号：US12877695

申请日：2010-09-08

Applicant: Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C11/00 ,  H01R43/00

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line

Abstract translation: 静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。 第一晶体管耦合在第一节点和第一位线之间。 第二晶体管耦合在第二节点和第二位线之间。 第三晶体管与第一节点耦合。 第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。 第五晶体管耦合在第三晶体管和第三位线之间

公开(公告)号：US20130258747A1

公开(公告)日：2013-10-03

申请号：US13437081

申请日：2012-04-02

Applicant: Jonathan Tsung-Yung CHANG ,  Cheng Hung LEE ,  Chung-Cheng CHOU ,  Hung-Jen LIAO ,  Bin-Hau LO

Inventor： Jonathan Tsung-Yung CHANG ,  Cheng Hung LEE ,  Chung-Cheng CHOU ,  Hung-Jen LIAO ,  Bin-Hau LO

IPC: G11C17/00 ,  G11C11/00 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C11/412 ,  G11C11/419

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

公开(公告)号：US20120206953A1

公开(公告)日：2012-08-16

申请号：US13025872

申请日：2011-02-11

Applicant: Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C5/06 ,  H01L25/00

CPC classification number: G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

Abstract translation: 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

公开(公告)号：US20100259999A1

公开(公告)日：2010-10-14

申请号：US12754733

申请日：2010-04-06

Applicant: Cheng Hung LEE ,  Ching-Wei WU ,  Bin SHENG ,  Hung-Jen LIAO

Inventor： Cheng Hung LEE ,  Ching-Wei WU ,  Bin SHENG ,  Hung-Jen LIAO

IPC: G11C7/00 ,  H03L5/00

CPC classification number: H01L27/1104 ,  G11C11/419

Abstract: A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.

Abstract translation: 集成电路的保持器包括具有与反相器的输出端耦合的第一栅极的第一晶体管。 第二晶体管与第一晶体管串联耦合。 第二晶体管具有与反相器的输入端耦合的第二栅极。

公开(公告)号：US20130188433A1

公开(公告)日：2013-07-25

申请号：US13354884

申请日：2012-01-20

Applicant: Chih-Yu LIN ,  Wei Min CHAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

Inventor： Chih-Yu LIN ,  Wei Min CHAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

IPC: G11C7/00

CPC classification number: G11C11/419

Abstract: A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.

Abstract translation: 电路包括第一节点，第二节点，存储器单元，第一数据线，第二数据线和写驱动器。 存储器单元耦合到第一节点和第二节点，并由第一节点处的第一电压和第二节点处的第二电压供电。 第一数据线和第二数据线耦合到存储器单元。 写入驱动器具有在写入操作期间承载小于第一电压的第三电压的第三节点。 写引导器耦合到第一数据线和第二数据线，并且被配置为在写操作期间，选择性地将第一数据线和第二数据线之一耦合到第三节点，并将第一数据中的另一个耦合 线和第二条数据线到第一个节点。

公开(公告)号：US20110194362A1

公开(公告)日：2011-08-11

申请号：US12702594

申请日：2010-02-09

Applicant: Chung-Ji LU ,  Lee-Cheng HUNG ,  Hung-Jen LIAO ,  Hsu-Shun CHEN ,  Hong-Chen CHENG ,  Chung-Yi Wu ,  Uppu Sharath CHANDRA

Inventor： Chung-Ji LU ,  Lee-Cheng HUNG ,  Hung-Jen LIAO ,  Hsu-Shun CHEN ,  Hong-Chen CHENG ,  Chung-Yi Wu ,  Uppu Sharath CHANDRA

IPC: G11C7/00 ,  G11C8/08

CPC classification number: G11C8/08 ,  G11C8/10

Abstract: A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array.

Abstract translation: 代表性电路装置包括具有电平移位器的本地控制电路，其中响应于接收到第一地址信号，电平移位器将第一地址信号从第一电压电平移位到第二电压电平，提供电平移位的第一地址信号 ; 以及具有用于接收多个地址信号的至少一个输入的字线驱动器，其中所述至少一个输入包括耦合到所述本地控制电路以接收所述电平移位的第一地址信号的第一输入，以及输出， 电耦合到存储单元阵列的字线。

公开(公告)号：US20140022852A1

公开(公告)日：2014-01-23

申请号：US13552692

申请日：2012-07-19

Applicant: Tzu-Kuei LIN ,  Jonathan Tsung-Yung CHANG ,  Hung-Jen LIAO ,  Yen-Huei CHEN ,  Jhon Jhy LIAW

Inventor： Tzu-Kuei LIN ,  Jonathan Tsung-Yung CHANG ,  Hung-Jen LIAO ,  Yen-Huei CHEN ,  Jhon Jhy LIAW

IPC: G11C8/16 ,  G11C7/10

CPC classification number: G11C7/1006 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412

Abstract: A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.

Abstract translation: 半导体存储器包括每个包括第一和第二端口的第一和第二存储器存储器锁存器。 第一对位线耦合到第一端口，并且第二对位线耦合到第二端口。 第一和第二对位线在第一和第二存储器锁存器之间被扭转。 第一读出放大器耦合到第一对位线，用于输出数据，第二读出放大器耦合到第二对位线，用于输出中间数据信号。 输出逻辑电路耦合到第二读出放大器的输出，并且被配置为基于中间数据信号和控制信号输出数据，该控制信号识别数据是否正在从第一存储器存储锁存器或第二存储器存储器锁存器中读取 。