公开(公告)号：US07746131B2

公开(公告)日：2010-06-29

申请号：US12344198

申请日：2008-12-24

Applicant: Cheng-Hsun Chan ,  Che-Li Lin

Inventor： Cheng-Hsun Chan ,  Che-Li Lin

IPC: H03L7/00

CPC classification number: H03K17/22 ,  H03K5/1252

Abstract: A reset signal filter includes a power voltage detector and a reset signal detector or includes only one reset signal detector. The power voltage detector includes a comparators and a basic logic gates (e.g. AND gate, OR gate, inverter, etc). The reset signal detector includes a comparator, N flip flops connected in series, an AND gate, an OR gate, a multiplexer and an output flip flop. The reset signal filter receives a first reset signal generated by a power voltage detector or a Schmitt trigger buffer and utilizes N flip flops to register the signal level of the first reset signal for N clock periods. Then the reset signal filter determines if the first rest signal is changed during N clock periods, and outputs a second reset signal.

Abstract translation: 复位信号滤波器包括电源电压检测器和复位信号检测器，或仅包括一个复位信号检测器。 电源电压检测器包括比较器和基本逻辑门（例如，与门，或门，反相器等）。 复位信号检测器包括比较器，串联连接的N个触发器，与门，或门，复用器和输出触发器。 复位信号滤波器接收由电源电压检测器或施密特触发缓冲器产生的第一复位信号，并利用N个触发器在N个时钟周期内对第一复位信号的信号电平进行寄存。 然后，复位信号滤波器确定在N个时钟周期期间是否改变第一个静止信号，并输出第二个复位信号。

公开(公告)号：US20090174438A1

公开(公告)日：2009-07-09

申请号：US12142755

申请日：2008-06-19

Applicant: Jin-Ho Lin ,  Cheng-Hsun Chan ,  Che-Li Lin

Inventor： Jin-Ho Lin ,  Cheng-Hsun Chan ,  Che-Li Lin

IPC: H03K5/22

CPC classification number: H03K17/22 ,  G06F1/24

Abstract: A data trigger reset device for an electronic device is provided in order to avoid system errors due to out-of-sequence reset on electronic devices of an electronic system. The data trigger reset device includes a voltage converter and a voltage comparator. The voltage converter receives an input signal and then converts the input signal to generate a data voltage signal. The voltage comparator is coupled to the voltage converter and is used for comparing the data voltage signal with a reference voltage to generate a reset signal for resetting the electronic device.

Abstract translation: 提供了一种用于电子设备的数据触发复位装置，以便避免由于电子系统的电子设备上的按顺序重置的系统错误。 数据触发复位装置包括电压转换器和电压比较器。 电压转换器接收输入信号，然后转换输入信号以产生数据电压信号。 电压比较器耦合到电压转换器，用于将数据电压信号与参考电压进行比较，以产生用于复位电子设备的复位信号。

公开(公告)号：US20100026357A1

公开(公告)日：2010-02-04

申请号：US12344198

申请日：2008-12-24

Applicant: Cheng-Hsun Chan ,  Che-Li Lin

Inventor： Cheng-Hsun Chan ,  Che-Li Lin

IPC: H03K3/02

CPC classification number: H03K17/22 ,  H03K5/1252

Abstract: A reset signal filter includes a power voltage detector and a reset signal detector or includes only one reset signal detector. The power voltage detector includes a comparators and a basic logic gates (e.g. AND gate, OR gate, inverter, etc). The reset signal detector includes a comparator, N flip flops connected in series, an AND gate, an OR gate, a multiplexer and an output flip flop. The reset signal filter receives a first reset signal generated by a power voltage detector or a Schmitt trigger buffer and utilizes N flip flops to register the signal level of the first reset signal for N clock periods. Then the reset signal filter determines if the first rest signal is changed during N clock periods, and outputs a second reset signal.

Abstract translation: 复位信号滤波器包括电源电压检测器和复位信号检测器，或仅包括一个复位信号检测器。 电源电压检测器包括比较器和基本逻辑门（例如，与门，或门，反相器等）。 复位信号检测器包括比较器，串联连接的N个触发器，与门，或门，复用器和输出触发器。 复位信号滤波器接收由电源电压检测器或施密特触发缓冲器产生的第一复位信号，并利用N个触发器在N个时钟周期内对第一复位信号的信号电平进行寄存。 然后，复位信号滤波器确定在N个时钟周期期间是否改变第一个静止信号，并输出第二个复位信号。

公开(公告)号：US08225166B2

公开(公告)日：2012-07-17

申请号：US12368182

申请日：2009-02-09

Applicant: Shun-An Yang ,  Che-Li Lin

Inventor： Shun-An Yang ,  Che-Li Lin

IPC: H03M13/00

CPC classification number: H03M13/3738 ,  H03M13/1165 ,  H03M13/15 ,  H03M13/152 ,  H03M13/2906 ,  H04H60/11 ,  H04L1/0057 ,  H04L1/0065 ,  H04L2001/0093

Abstract: A signal processing apparatus is provided. The signal processing apparatus includes an inner-code decoder, an outer-code decoder, and an error detection unit. The inner-code decoder decodes an input data stream to generate a first output data stream, wherein the input data stream is coded using a concatenated coding scheme including an outer coding and an inner coding. The outer-code decoder decodes the first output data stream to generate a second output data stream. The error detection unit performs an error detection upon the second output data stream to generate an error detection result. The decision logic sets error indication information of the second output data stream according to at least the error detection result.

Abstract translation: 提供一种信号处理装置。 信号处理装置包括内码解码器，外码解码器和错误检测单元。 内码解码器解码输入数据流以产生第一输出数据流，其中使用包括外部编码和内部编码的级联编码方案对输入数据流进行编码。 外码解码器解码第一输出数据流以产生第二输出数据流。 错误检测单元对第二输出数据流执行错误检测以产生错误检测结果。 决定逻辑至少根据错误检测结果来设定第二输出数据流的错误指示信息。

公开(公告)号：US07787848B2

公开(公告)日：2010-08-31

申请号：US11858111

申请日：2007-09-19

Applicant: Che-Li Lin ,  Hua-Shan Chou ,  Tsung-Han Wu

Inventor： Che-Li Lin ,  Hua-Shan Chou ,  Tsung-Han Wu

IPC: H04B1/06

CPC classification number: H04N5/52 ,  H03G3/3068 ,  H04N5/4401 ,  H04N21/4263

Abstract: A gain control method which includes setting a first initial gain value to a first variable gain amplifier; measuring a first power value corresponding to incoming signals; measuring a second power value corresponding to a target signal; and resetting the first initial gain value according to the first power value and the second power value. Another gain control method is also disclosed, which includes updating a gain value of a first variable gain amplifier by combining an adjustment value with the gain value according to a first tuning direction; obtaining a signal quality indicator; comparing the signal quality indicator with a reference signal quality indicator to generate a comparison result; and referring to the comparison result, further updating the gain value according to the first tuning direction or a second tuning direction opposite to the first tuning direction.

Abstract translation: 一种增益控制方法，包括：将第一初始增益值设置为第一可变增益放大器; 测量对应于输入信号的第一功率值; 测量对应于目标信号的第二功率值; 以及根据所述第一功率值和所述第二功率值来重置所述第一初始增益值。 还公开了另一种增益控制方法，其包括通过根据第一调谐方向组合调整值与增益值来更新第一可变增益放大器的增益值; 获得信号质量指标; 将信号质量指示符与参考信号质量指标进行比较以产生比较结果; 参照比较结果，根据与第一调谐方向相反的第一调谐方向或第二调谐方向进一步更新增益值。

公开(公告)号：US20090279649A1

公开(公告)日：2009-11-12

申请号：US12208354

申请日：2008-09-11

Applicant: Wen-Yuan Tsao ,  Che-Li Lin ,  Chi-Ming Yuan

Inventor： Wen-Yuan Tsao ,  Che-Li Lin ,  Chi-Ming Yuan

IPC: H04L7/00

CPC classification number: H04L7/10 ,  G09G5/008 ,  H04L7/0008 ,  H04L7/06

Abstract: A data synchronization method for a transmitter of a display device includes utilizing a plurality of first signaling line sets to couple the transmitter and a plurality of receivers in a dedicated type manner, transmitting a synchronization signal to the plurality of receivers according to a transistor-to-transistor logic signal form, transmitting a synchronization start-up signal to the plurality of receivers via the plurality of first signaling line sets a first time later after the synchronization signal is transmitted, and then transmitting a data signal to the plurality of receivers via the plurality of first signaling line sets a second time later after the synchronization start-up signal is transmitted. The synchronization signal has a longer effective time than the synchronization start-up signal.

Abstract translation: 一种用于显示设备的发射机的数据同步方法包括利用多个第一信令线路集合以专用类型方式耦合发射机和多个接收机，根据晶体管与基站发送同步信号给多个接收机 晶体管逻辑信号形式，在发送同步信号之后的第一次之后经由多个第一信令线集合向多个接收器发送同步启动信号，然后经由该多个接收器发送数据信号 多个第一信令线在发送同步启动信号之后第二次设置。 同步信号具有比同步启动信号更长的有效时间。

公开(公告)号：US20090274241A1

公开(公告)日：2009-11-05

申请号：US12175463

申请日：2008-07-18

Applicant: Wen-Yuan Tsao ,  Che-Li Lin

Inventor： Wen-Yuan Tsao ,  Che-Li Lin

IPC: H04L27/00

CPC classification number: H04L25/0272 ,  G09G3/3611 ,  G09G3/3688 ,  G09G5/18 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2320/0219

Abstract: In order to resolve problems of clock and data skews in transmission signals in a display device, the present invention provides a data transmission device including a timing controller, a plurality of source drivers and a plurality of transmission line sets. The timing controller generates a plurality of definable signals each generating at least four voltage levels. The plurality of source drivers receives the plurality of definable signals. The plurality of transmission line sets are coupled between the timing controller and the plurality of source drivers and used for transmitting the plurality of definable signals. Preferably, the plurality of definable signals are differential signals.

Abstract translation: 为了解决显示装置中的传输信号中的时钟和数据偏移的问题，本发明提供一种包括定时控制器，多个源驱动器和多个传输线组的数据传输装置。 定时控制器产生多个可定义的信号，每个信号产生至少四个电压电平。 多个源极驱动器接收多个可定义的信号。 多个传输线组耦合在定时控制器和多个源极驱动器之间，并用于传输多个可定义的信号。 优选地，多个可定义信号是差分信号。

公开(公告)号：US20080126915A1

公开(公告)日：2008-05-29

申请号：US11562993

申请日：2006-11-23

Applicant: Chih-Peng Chang ,  Che-Li Lin

Inventor： Chih-Peng Chang ,  Che-Li Lin

IPC: H03M13/00

CPC classification number: H04L1/0045

Abstract: A DVB-H receiver for performing forward error correction is disclosed. The DVB-H receiver includes: a tuner, for receiving a data stream; a base-band receiver, coupled to the tuner, for continuously extracting and transmitting data bytes of an MPE-FEC frame from the data stream; a backend system, coupled to the base-band receiver, for generating corresponding syndromes of the extracted data bytes once all data bytes of the MPE-FEC frame are received, outputting the syndromes to the base-band receiver, and forward error correcting the MPE-FEC frame according to error values corresponding to the syndromes; and a storage device, coupled to the backend system, for storing the extracted data bytes. The base-band receiver generates the error values and error locations according to the received syndromes, and then outputs the error values and error locations to the backend system.

Abstract translation: 公开了一种用于执行前向纠错的DVB-H接收机。 DVB-H接收机包括：用于接收数据流的调谐器; 耦合到所述调谐器的基带接收器，用于从所述数据流连续提取和发送MPE-FEC帧的数据字节; 后端系统耦合到基带接收机，用于在接收到MPE-FEC帧的所有数据字节之后产生所提取的数据字节的相应校正子，将校验子输出到基带接收机，以及前向纠错MPE -FEC帧根据对应于综合征的误差值; 以及耦合到后端系统的用于存储所提取的数据字节的存储设备。 基带接收机根据接收到的校正子生成错误值和错误位置，然后将错误值和错误位置输出到后端系统。

公开(公告)号：US20070229338A1

公开(公告)日：2007-10-04

申请号：US11695051

申请日：2007-04-01

Applicant: Wen-Yuan Tsao ,  Chang-San Chen ,  Che-Li Lin

Inventor： Wen-Yuan Tsao ,  Chang-San Chen ,  Che-Li Lin

IPC: H03M1/66 ,  H03M1/12

CPC classification number: G09G3/3688 ,  G09G2310/027 ,  G09G2330/021 ,  H03M1/002 ,  H03M1/66

Abstract: A method capable of reducing power consumption of source drivers is disclosed. The method includes a reference voltage source charging or discharging a loading end of a source driver to a reference voltage having a polarity the same as a polarity of a target voltage and a voltage level near a voltage level of the target voltage, and an output stage of the source driver charging or discharging the loading end to the target voltage.

Abstract translation: 公开了一种能够降低源驱动器功耗的方法。 该方法包括将源极驱动器的负载端充电或放电到具有与目标电压的极性相同的极性的参考电压和接近目标电压的电压电平的电压电平的参考电压源，以及输出级 的源极驱动器将负载端充电或放电到目标电压。

公开(公告)号：US20070182690A1

公开(公告)日：2007-08-09

申请号：US11467924

申请日：2006-08-29

Applicant: Che-Li Lin

Inventor： Che-Li Lin

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2370/08

Abstract: A receiver for an LCD source driver of an LCD panel includes a converter, a comparing circuit and a decoding circuit. The converter converts two pairs of differential current signals into two pairs of differential voltage signals. The comparing circuit is coupled to the converter for generating reference signals based on differences between the two pairs of differential voltage signals. The decoding circuit is coupled to the comparing circuit for generating data signals, clock signal, setting signals, and control signals based the reference signals.

Abstract translation: 用于LCD面板的LCD源驱动器的接收器包括转换器，比较电路和解码电路。 转换器将两对差分电流信号转换成两对差分电压信号。 比较电路耦合到转换器，用于基于两对差分电压信号之间的差异产生参考信号。 解码电路耦合到比较电路，用于基于参考信号产生数据信号，时钟信号，设置信号和控制信号。