公开(公告)号：US06853417B2

公开(公告)日：2005-02-08

申请号：US10178523

申请日：2002-06-25

Applicant: Chin-Cheng Chien ,  Cheng-Jen Chu

Inventor： Chin-Cheng Chien ,  Cheng-Jen Chu

IPC: G02B5/02 ,  G02B5/08 ,  G02F1/1335 ,  G03F1/00 ,  G03F1/70 ,  G03F7/20

CPC classification number: G02F1/133553

Abstract: A method of fabricating a slant reflector with a bump structure, includes the steps of: providing a substrate; forming a layer of photosensitive material on the substrate; patterning the photosensitive material to form a plurality of trapezoidal bumps that have different bottom areas and that are joined to each other at their bottoms; and smoothing the trapezoidal bumps to form a bump structure with an inclined angle. The invention utilizes a photo-mask with a particular pattern and optical diffraction to fabricate the bump structure in a simple way.

Abstract translation: 制造具有凸块结构的倾斜反射体的方法包括以下步骤：提供基板; 在基板上形成感光材料层; 图案化感光材料以形成具有不同底部区域并且在其底部彼此连接的多个梯形凸块; 并平滑梯形凸块以形成具有倾斜角的凸块结构。 本发明利用具有特定图案和光学衍射的光掩模以简单的方式制造凸块结构。

公开(公告)号：US06891591B2

公开(公告)日：2005-05-10

申请号：US10271747

申请日：2002-10-17

Applicant: Cheng-Jen Chu ,  Chin-Cheng Chien

Inventor： Cheng-Jen Chu ,  Chin-Cheng Chien

IPC: G02B5/08 ,  F21V7/22 ,  G02B5/09 ,  G02F1/1335 ,  G02F1/1345 ,  G02F1/13

CPC classification number: G02B5/09 ,  F21V7/22 ,  G02F1/133553

Abstract: A method of fabricating slant reflector with bump structure, at least comprising the steps of: providing a substrate; forming a photosensitivity material layer on the substrate; patterning the photosensitivity material layer to form m groups of pattern (m≧1, m is positive integral), and each group of pattern includes a plurality of bumps with different bottom area; and jointing the bumps to form a slant surface with bump structure. The photosensitivity material layer is either orderly or randomly patterned to form m groups of patterns. The step of patterning the photosensitivity material layer includes exposing and developing. The invention utilizes one photo-mask with particular pattern to fabricate the bump structure in a simple way.

Abstract translation: 一种制造具有凸块结构的倾斜反射体的方法，至少包括以下步骤：提供基底; 在基板上形成感光材料层; 图案化感光材料层以形成m组图案（m> = 1，m为正整数），并且每组图案包括具有不同底部面积的多个凸块; 并且接合凸起以形成具有凸起结构的倾斜表面。 光敏材料层是有序的或随机地图案化以形成m组图案。 图案化感光材料层的步骤包括曝光和显影。 本发明利用具有特定图案的一个光掩模以简单的方式制造凸块结构。

公开(公告)号：US09318567B2

公开(公告)日：2016-04-19

申请号：US13603425

申请日：2012-09-05

Applicant: Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC: H01L21/31 ,  H01L21/84 ,  H01L21/311 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.

Abstract translation: 制造半导体器件的方法包括以下步骤。 首先，提供至少包括翅片结构和至少设置在其上的栅极半导体层的半导体衬底。 栅极半导体层覆盖翅片结构的一部分。 然后沉积牺牲层以完全覆盖翅片结构。 随后，翅片结构的顶表面通过蚀刻工艺从牺牲层露出。 然后沉积材料层，其共形地覆盖栅极半导体层，鳍结构和牺牲层。 最后，蚀刻材料层直到翅片结构的顶表面露出，并且在栅极半导体层的侧表面上同时形成第一间隔物。

公开(公告)号：US08980753B2

公开(公告)日：2015-03-17

申请号：US12886580

申请日：2010-09-21

Applicant: Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

Inventor： Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L21/823814

Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有第一晶体管区域和第二晶体管区域的衬底; 在第一晶体管区域上形成第一金属氧化物半导体（MOS）晶体管，在第二晶体管区域形成第二MOS晶体管，其中第一MOS晶体管包括第一虚拟栅极，第二MOS晶体管包括第二虚拟栅极; 在所述第二MOS晶体管上形成图案化的硬掩模，其中所述硬掩模包括至少一个金属原子; 以及使用图案化的硬掩模去除第一MOS晶体管的第一伪栅极。

公开(公告)号：US08754448B2

公开(公告)日：2014-06-17

申请号：US13286222

申请日：2011-11-01

Applicant: Chin-I Liao ,  Teng-Chun Hsuan ,  Chin-Cheng Chien

Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  Chin-Cheng Chien

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.

Abstract translation: 半导体器件包括半导体衬底和多个晶体管。 半导体衬底至少包括一个iso区域（即开放区域）和至少一个致密区域。 晶体管分别设置在iso区域和致密区域中。 每个晶体管至少包括一个源极/漏极区域。 源极/漏极区域包括具有底部厚度和侧部厚度的第一外延层，并且底部厚度基本上大于或等于侧部厚度。

公开(公告)号：US20130270612A1

公开(公告)日：2013-10-17

申请号：US13447286

申请日：2012-04-16

Applicant: Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

Abstract translation: 本发明提供一种非平面FET，其包括衬底，鳍结构，栅极和栅极电介质层。 翅片结构设置在基板上。 翅片结构包括与基底相邻的第一部分，其中第一部分朝向基底的一侧收缩。 门设置在翅片结构上。 栅介质层设置在鳍结构和栅极之间。 本发明还提供一种制造非平面FET的方法。

公开(公告)号：US08551829B2

公开(公告)日：2013-10-08

申请号：US12943015

申请日：2010-11-10

Applicant: Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/70

CPC classification number: H01L29/66795

Abstract: A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.

Abstract translation: 一种制造多栅极晶体管器件的方法包括：提供其上形成有第一图案化半导体层的半导体衬底，顺序地形成栅极电介质层和覆盖半导体衬底上的第一图案化半导体层的一部分的栅极层， 以形成第二图案化半导体层，并且执行选择性外延生长工艺以在第二图案化半导体层的表面上形成外延层。

公开(公告)号：US20130193585A1

公开(公告)日：2013-08-01

申请号：US13363390

申请日：2012-02-01

Applicant: Chin-Fu Lin ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien

Inventor： Chin-Fu Lin ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien

IPC: H01L23/48 ,  H01L21/302

CPC classification number: H01L21/3085 ,  H01L21/3086 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

公开(公告)号：US20130105861A1

公开(公告)日：2013-05-02

申请号：US13286222

申请日：2011-11-01

Applicant: Chin-I Liao ,  Teng-Chun Hsuan ,  Chin-Cheng Chien

Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  Chin-Cheng Chien

IPC: H01L21/205 ,  H01L27/088

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.

Abstract translation: 半导体器件包括半导体衬底和多个晶体管。 半导体衬底至少包括一个iso区域（即开放区域）和至少一个致密区域。 晶体管分别设置在iso区域和致密区域中。 每个晶体管至少包括一个源极/漏极区域。 源极/漏极区域包括具有底部厚度和侧部厚度的第一外延层，并且底部厚度基本上大于或等于侧部厚度。

公开(公告)号：US20130078780A1

公开(公告)日：2013-03-28

申请号：US13241188

申请日：2011-09-22

Applicant: Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien ,  Chun-Yuan Wu

Inventor： Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/28229 ,  H01L29/517 ,  H01L29/78

Abstract: A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成中间层。 在中间层上形成第一金属氧化物层。 进行还原处理以将第一金属氧化物层还原成金属层。 执行高温处理以将金属层转变为第二金属氧化物层。