公开(公告)号：US20080245774A1

公开(公告)日：2008-10-09

申请号：US12157209

申请日：2008-06-09

申请人： Cheol-Hee Kim ,  Nam-Hyun Kang ,  Jun-Ki Kim ,  Chang-Woo Lee

发明人： Cheol-Hee Kim ,  Nam-Hyun Kang ,  Jun-Ki Kim ,  Chang-Woo Lee

IPC分类号： B23K26/00 ,  B23K9/00

CPC分类号： B23K28/02 ,  B23K26/0093 ,  B23K26/348

摘要： The present invention relates to a laser-rotating arc hybrid welding system and a welding method using the system. The laser-rotating arc hybrid welding system of the present invention includes an arc discharge unit (2) for generating arc discharge along an area to be welded. A laser generation unit (4) radiates laser light onto the area to be welded. A rotating device (24) rotates the arc discharge unit (2). In the welding method using the laser-rotating arc hybrid welding system, a plurality of parent metals is aligned with a welding location. A laser-rotating arc hybrid welding system is located with respect to an area to be welded, arc discharge is generated while an arc discharge unit is rotated at a predetermined turning radius, and laser light is subsequently radiated using a laser generation unit.

摘要翻译： 本发明涉及激光旋转电弧复合焊接系统和使用该系统的焊接方法。 本发明的激光旋转电弧复合焊接系统包括：沿着待焊接区域产生电弧放电的电弧放电单元（2）。 激光产生单元（4）将激光照射到待焊接的区域上。 旋转装置（24）使电弧放电单元（2）旋转。 在使用激光旋转电弧复合焊接系统的焊接方法中，多个母体金属与焊接位置对准。 激光旋转电弧复合焊接系统相对于待焊接的区域定位，在电弧放电单元以预定转动半径旋转时产生电弧放电，并且随后使用激光产生单元辐射激光。

公开(公告)号：US08963205B2

公开(公告)日：2015-02-24

申请号：US12165164

申请日：2008-06-30

申请人： Yong-Soo Kim ,  Jun-Ki Kim ,  Se-Aug Jang

发明人： Yong-Soo Kim ,  Jun-Ki Kim ,  Se-Aug Jang

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/66651 ,  H01L29/7843

摘要： A transistor of a semiconductor device includes a substrate, a gate over the substrate, a source/drain region formed in the substrate to have a channel region therebetween, and an epitaxial layer formed below the channel region to have a different lattice constant from the substrate. The epitaxial layer having a different lattice constant with a substrate material is formed below the channel region to apply a stress to the channel region. Thus, the mobility of carriers of the transistor increases.

摘要翻译： 半导体器件的晶体管包括衬底，衬底上的栅极，形成在衬底中以在其间具有沟道区的源极/漏极区和形成在沟道区下方的与衬底不同的晶格常数的外延层 。 在沟道区的下方形成具有与衬底材料不同的晶格常数的外延层，以对沟道区施加应力。 因此，晶体管的载流子的迁移率增加。

公开(公告)号：US20090121235A1

公开(公告)日：2009-05-14

申请号：US12165164

申请日：2008-06-30

申请人： Yong-Soo KIM ,  Jun-Ki Kim

发明人： Yong-Soo KIM ,  Jun-Ki Kim

IPC分类号： H01L29/24 ,  H01L29/778 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/66651 ,  H01L29/7843

摘要： A transistor of a semiconductor device includes a substrate, a gate over the substrate, a source/drain region formed in the substrate to have a channel region therebetween, and an epitaxial layer formed below the channel region to have a different lattice constant from the substrate. The epitaxial layer having a different lattice constant with a substrate material is formed below the channel region to apply a stress to the channel region. Thus, the mobility of carriers of the transistor increases.

摘要翻译： 半导体器件的晶体管包括衬底，衬底上的栅极，形成在衬底中以在其间具有沟道区的源极/漏极区和形成在沟道区下方的与衬底不同的晶格常数的外延层 。 在沟道区的下方形成具有与衬底材料不同的晶格常数的外延层，以对沟道区施加应力。 因此，晶体管的载流子的迁移率增加。

公开(公告)号：US6057228A

公开(公告)日：2000-05-02

申请号：US140834

申请日：1998-08-26

申请人： Seung-Yun Lee ,  Yong-Sup Hwang ,  Chong-Ook Park ,  Dong-Won Kim ,  Sa-Kyun Rha ,  Jun-Ki Kim

发明人： Seung-Yun Lee ,  Yong-Sup Hwang ,  Chong-Ook Park ,  Dong-Won Kim ,  Sa-Kyun Rha ,  Jun-Ki Kim

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/00

CPC分类号： H01L21/76838 ,  H01L23/53228 ,  H01L2924/0002

摘要： The present invention relates to a method of forming an interconnection for a semiconductor device using copper. The method of the invention, including the steps of forming an insulating layer having a groove on a semiconductor substrate containing active elements; forming and depositing a copper thin film on the insulating layer including the groove; and reflowing the copper thin film, may reflow the copper thin film deposited on the semiconductor substrate having a high-step surface for less than 30 min. below 450.degree. C., which show improved annealing conditions as compared with the conventional art. In addition, by reducing consumption of thermal energy in accordance with a low-temperature process, copper is restrained from being rapidly diffused through a silicon substrate, electrodes, etc. when forming the interconnection for the semiconductor device, thus improving productivity of the semiconductor devices.

摘要翻译： 本发明涉及使用铜形成半导体器件互连的方法。 本发明的方法包括以下步骤：在包含有源元件的半导体衬底上形成具有凹槽的绝缘层; 在包括所述槽的所述绝缘层上形成和沉积铜薄膜; 并且回流铜薄膜时，可以使沉积在具有高阶表面的半导体衬底上的铜薄膜回流少于30分钟。 低于450℃，与现有技术相比显示出改善的退火条件。 此外，通过根据低温处理减少热能消耗，在形成半导体器件的互连时，抑制铜通过硅衬底，电极等快速扩散，从而提高半导体器件的生产率 。

公开(公告)号：US06080615A

公开(公告)日：2000-06-27

申请号：US2679

申请日：1998-01-05

申请人： Chang-Jae Lee ,  Jun-Ki Kim

发明人： Chang-Jae Lee ,  Jun-Ki Kim

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/105 ,  H01L21/8242

CPC分类号： H01L28/40 ,  H01L27/0629

摘要： A method for fabricating an integrated circuit includes the steps of forming an isolating insulation film on a portion of a semiconductor substrate, forming a gate insulating film, a first conductive layer, an insulating film and a second conductive layer successively on the semiconductor substrate including the isolating insulation film, selectively removing the second conductive layer and the insulating film to pattern an upper electrode of a capacitor in a capacitor forming region and a dummy gate electrode in a transistor forming region, respectively, forming a lower electrode mask in the capacitor forming region, and selectively removing the first conductive layer and the gate insulating film by using the lower electrode mask and the dummy gate electrode as masks, to form a lower electrode of the capacitor and the gate electrode of the transistor.

摘要翻译： 一种用于制造集成电路的方法包括以下步骤：在半导体衬底的一部分上形成隔离绝缘膜，在半导体衬底上依次形成栅绝缘膜，第一导电层，绝缘膜和第二导电层， 隔离绝缘膜，选择性地去除第二导电层和绝缘膜，以分别在晶体管形成区域中的电容器形成区域中的电容器的上电极和伪栅极电极，以在电容器形成区域中形成下电极掩模 并且通过使用下电极掩模和伪栅极作为掩模来选择性地去除第一导电层和栅极绝缘膜，以形成电容器的下电极和晶体管的栅电极。

公开(公告)号：US20130323307A1

公开(公告)日：2013-12-05

申请号：US13984756

申请日：2012-02-13

申请人： Hong-Ryeol Jeon ,  Bong-Sang Lee ,  Su-Jun Park ,  Bong-Geun Cha ,  Jun-Ki Kim

发明人： Hong-Ryeol Jeon ,  Bong-Sang Lee ,  Su-Jun Park ,  Bong-Geun Cha ,  Jun-Ki Kim

IPC分类号： A61K9/70 ,  A61K31/522

CPC分类号： A61K9/7007 ,  A61K9/0056 ,  A61K9/006 ,  A61K9/14 ,  A61K31/519 ,  A61K31/522

摘要： The present invention provides a method for preparing a film comprising a high amount of a sildenafil free base uniformly dispersed therein and having a suitable thickness and size, as well as flexibility providing good handling stability and being not prone to breaking. The present invention also provides a sildenafil free base-containing film prepared from the method.

摘要翻译： 本发明提供了一种制备包含大量均匀分散在其中并具有合适的厚度和尺寸的西地那新游离碱的膜的方法，以及提供良好的操作稳定性并且不易于破裂的柔软性。 本发明还提供了由该方法制备的含西地那非游离碱的膜。

公开(公告)号：US07338871B2

公开(公告)日：2008-03-04

申请号：US11020494

申请日：2004-12-21

申请人： Joo-Wan Lee ,  Jun-Ki Kim

发明人： Joo-Wan Lee ,  Jun-Ki Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/76877 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4975

摘要： The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conductive region including a conductive pattern and silicon, and preventing an increase in a parasitic capacity of the conductive pattern according to an increase in a thickness of a barrier layer.

摘要翻译： 本发明提供一种制造半导体器件的方法，该半导体器件能够在形成与包括导电图案和硅的N型导电区域直接接触的导电图案期间防止在与N型导电区域接触的区域中的接触电阻增加 并且根据阻挡层的厚度的增加防止导电图案的寄生电容的增加。

公开(公告)号：US09907759B2

公开(公告)日：2018-03-06

申请号：US13984756

申请日：2012-02-13

申请人： Hong-Ryeol Jeon ,  Bong-Sang Lee ,  Su-Jun Park ,  Bong-Geun Cha ,  Jun-Ki Kim

发明人： Hong-Ryeol Jeon ,  Bong-Sang Lee ,  Su-Jun Park ,  Bong-Geun Cha ,  Jun-Ki Kim

IPC分类号： A61K9/14 ,  A61L9/04 ,  A61K31/496 ,  A61K9/19 ,  A61K9/20 ,  A61K9/00 ,  A61K9/70 ,  A61K31/519 ,  A61K31/522

CPC分类号： A61K9/7007 ,  A61K9/0056 ,  A61K9/006 ,  A61K9/14 ,  A61K31/519 ,  A61K31/522

摘要： The present invention provides a method for preparing a film comprising a high amount of a sildenafil free base uniformly dispersed therein and having a suitable thickness and size, as well as flexibility providing good handling stability and being not prone to breaking. The present invention also provides a sildenafil free base-containing film prepared from the method.

公开(公告)号：US08642466B2

公开(公告)日：2014-02-04

申请号：US13607012

申请日：2012-09-07

申请人： Jun-Ki Kim

发明人： Jun-Ki Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10885

摘要： A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming multiple layers of spacer layers with a capping layer interposed therebetween over the bit line structures, exposing a surface of the substrate by selectively etching the spacer layers, forming air gaps and capping spacers for covering upper portions of the air gaps by selectively etching the capping layer, and forming storage node contact plugs between the bit line structures.

摘要翻译： 一种用于制造半导体器件的方法包括在衬底上形成多个位线结构，在位线结构之间形成多层间隔层，其中封盖层介于其间，通过选择性地蚀刻间隔层而露出衬底的表面， 通过选择性地蚀刻覆盖层形成气隙和封盖间隔物，以覆盖气隙的上部，以及在位线结构之间形成储存节点接触塞。

公开(公告)号：US20050287799A1

公开(公告)日：2005-12-29

申请号：US11020494

申请日：2004-12-21

申请人： Joo-Wan Lee ,  Jun-Ki Kim

发明人： Joo-Wan Lee ,  Jun-Ki Kim

IPC分类号： H01L27/108 ,  H01L21/285 ,  H01L21/425 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L29/49

CPC分类号： H01L21/76877 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4975

摘要： The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conductive region including a conductive pattern and silicon, and preventing an increase in a parasitic capacity of the conductive pattern according to an increase in a thickness of a barrier layer.

摘要翻译： 本发明提供一种制造半导体器件的方法，该半导体器件能够在形成与包括导电图案和硅的N型导电区域直接接触的导电图案期间防止在与N型导电区域接触的区域中的接触电阻增加 并且根据阻挡层的厚度的增加防止导电图案的寄生电容的增加。