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    Method for fabricating a semiconductor device
    1.
    发明授权
    Method for fabricating a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US08963205B2

    公开(公告)日：2015-02-24

    申请号：US12165164

    申请日：2008-06-30

    申请人： Yong-Soo Kim ,  Jun-Ki Kim ,  Se-Aug Jang

    发明人： Yong-Soo Kim ,  Jun-Ki Kim ,  Se-Aug Jang

    IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/78

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/66651 ,  H01L29/7843

    摘要： A transistor of a semiconductor device includes a substrate, a gate over the substrate, a source/drain region formed in the substrate to have a channel region therebetween, and an epitaxial layer formed below the channel region to have a different lattice constant from the substrate. The epitaxial layer having a different lattice constant with a substrate material is formed below the channel region to apply a stress to the channel region. Thus, the mobility of carriers of the transistor increases.

    摘要翻译： 半导体器件的晶体管包括衬底，衬底上的栅极，形成在衬底中以在其间具有沟道区的源极/漏极区和形成在沟道区下方的与衬底不同的晶格常数的外延层 。 在沟道区的下方形成具有与衬底材料不同的晶格常数的外延层，以对沟道区施加应力。 因此，晶体管的载流子的迁移率增加。

    SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METAL CONTACTS, AND METHODS OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METAL CONTACTS, AND METHODS OF FABRICATING THE SAME 有权
    包括电容器和金属接触件的半导体器件及其制造方法

    公开(公告)号：US20120205779A1

    公开(公告)日：2012-08-16

    申请号：US13337481

    申请日：2011-12-27

    申请人： Jun Ki KIM

    发明人： Jun Ki KIM

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L28/60 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

    摘要： Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 该方法包括在单元区域和周边区域中形成第一模具层，形成穿过单元区域中的第一模具层的第一存储节点和在周边区域中贯穿第一模具层的第一触点，形成第二模具 形成在第一模具层上的第二存储节点，形成穿过第二模具层的第二存储节点，以连接到第一存储节点中的相应的第一存储节点，将单元区域中的第二模具层和单元区域中的第一模具层移除到 离开第一模具层在周边区域，并形成穿过第一层间绝缘层以连接到第一触点的第二触点。 还提供了相关设备。

    Method for manufacturing semiconductor device capable of increasing current drivability of PMOS transistor
    5.
    发明授权
    Method for manufacturing semiconductor device capable of increasing current drivability of PMOS transistor 失效
    能够提高PMOS晶体管的电流驱动能力的半导体器件的制造方法

    公开(公告)号：US07858489B2

    公开(公告)日：2010-12-28

    申请号：US12118264

    申请日：2008-05-09

    申请人： Jun Ki Kim

    发明人： Jun Ki Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224 ,  H01L29/78 ,  H01L29/7846

    摘要： A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor substrate such that compressive stress is applied in a channel length direction of a PMOS transistor by oxidizing the buffer layer; removing portions of the insulation layer and thereby forming an isolation layer; and forming the PMOS transistor on the PMOS region of the semiconductor substrate.

    摘要翻译： 通过在具有PMOS区域的半导体衬底中限定沟槽，能够选择性地施加不同应力以提高PMOS晶体管的电流驱动能力的半导体器件; 在沟槽的侧壁上选择性地形成缓冲层; 形成绝缘层以填充沟槽; 退火半导体衬底，使得通过氧化缓冲层在PMOS晶体管的沟道长度方向施加压应力; 去除绝缘层的部分，从而形成隔离层; 以及在半导体衬底的PMOS区上形成PMOS晶体管。

    SEMICONDUCTOR DEVICE HAVING A REDUCED FUSE THICKNESS AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE HAVING A REDUCED FUSE THICKNESS AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    具有减小的熔丝厚度的半导体器件及其制造方法

    公开(公告)号：US20090267180A1

    公开(公告)日：2009-10-29

    申请号：US12245318

    申请日：2008-10-03

    申请人： Jun Ki KIM

    发明人： Jun Ki KIM

    IPC分类号： H01L21/768 ,  H01L23/525

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device that has a reduced fuse thickness without compromising the bondability of an associated pad and a method for manufacturing the same is described. The semiconductor device includes a pad and a fuse formed on a planar level. The pad and fuse are formed using a metal according to the metal used for the planar level on which the pad and fuse are formed. The pad is formed such that the center portion of the pad is positioned lower than that of the fuse. During the opening of the pad, the thickness of the fuse is reduced without reducing the thickness of the pad. A subsequent repair process can then be easily performed on the fuse having the reduced thickness without degrading the bondability of the pad.

    摘要翻译： 描述了具有减小的熔丝厚度而不损害相关焊盘的可焊接性的半导体器件及其制造方法。 半导体器件包括形成在平面级上的焊盘和熔丝。 焊盘和熔丝使用根据用于形成焊盘和熔丝的平面级的金属的金属形成。 焊盘形成为使得焊盘的中心部分定位成低于保险丝的中心部分。 在焊盘打开期间，熔丝的厚度减小而不减小焊盘的厚度。 然后可以容易地对具有减小的厚度的熔丝执行随后的修复过程，而不降低焊盘的可焊接性。

    Transistor and method for fabricating the same
    7.
    发明申请
    Transistor and method for fabricating the same 有权
    晶体管及其制造方法

    公开(公告)号：US20060273381A1

    公开(公告)日：2006-12-07

    申请号：US11157999

    申请日：2005-06-21

    申请人： Jun Ki Kim ,  Soo Hyun Kim ,  Hyun Chul Sohn ,  Se Aug Jang

    发明人： Jun Ki Kim ,  Soo Hyun Kim ,  Hyun Chul Sohn ,  Se Aug Jang

    IPC分类号： H01L29/94

    CPC分类号： H01L29/66795 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/7853

    摘要： Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.

    摘要翻译： 公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。 该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层 去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域， 对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

    Method for forming a wiring metal layer in a semiconductor device
    8.
    发明授权
    Method for forming a wiring metal layer in a semiconductor device 失效
    在半导体器件中形成布线金属层的方法

    公开(公告)号：US5804501A

    公开(公告)日：1998-09-08

    申请号：US910037

    申请日：1997-08-12

    申请人： Jun Ki Kim

    发明人： Jun Ki Kim

    IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L21/28

    CPC分类号： H01L21/76877

    摘要： A method for forming a wiring layer for a semiconductor device is disclosed. During the formation of a VLSI-scale device having a contact hole with a large aspect ratio, metal layers are filled into the contact hole without spatial discontinuities, and a first wiring metal deposition process is carried out by applying a chemical vapor deposition (CVD) process. Compared with a conventional method, even if a thin film of aluminum is deposited, the wiring metal film can be deposited into the contact hole without spatial discontinuities. The upper opening of the contact hole may remain wide after deposition of the first wiring layer, and the wiring metal atoms may easily move into the contact hole upon reaching the wafer during a second wiring metal deposition. The disclosed invention may provide for superior wiring metal filling characteristics as compared with conventional methods. Further, the first wiring metal deposition may be carried out within a short period of time as compared with the conventional method, and the productivity may be improved.

    摘要翻译： 公开了一种用于形成半导体器件的布线层的方法。 在形成具有大纵横比的接触孔的VLSI标尺装置的过程中，将金属层填充到接触孔中而没有空间不连续性，并且通过施加化学气相沉积（CVD）来进行第一布线金属沉积工艺， 处理。 与常规方法相比，即使沉积铝薄膜，也可以将布线金属膜沉积到接触孔中而没有空间不连续性。 在第一布线层沉积之后，接触孔的上开口可以保持宽，并且布线金属原子在第二布线金属沉积期间到达晶片时容易移动到接触孔中。 所公开的发明可以提供与常规方法相比优异的布线金属填充特性。 此外，与常规方法相比，第一布线金属沉积可以在短时间内进行，并且可以提高生产率。

    METHOD FOR MANUFACTURING VERTICAL TRANSISTOR HAVING ONE SIDE CONTACT
    10.
    发明申请
    METHOD FOR MANUFACTURING VERTICAL TRANSISTOR HAVING ONE SIDE CONTACT 审中-公开
    用于制造具有单面接触的垂直晶体管的方法

    公开(公告)号：US20120135573A1

    公开(公告)日：2012-05-31

    申请号：US13160689

    申请日：2011-06-15

    申请人： Jun Ki KIM

    发明人： Jun Ki KIM

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/2257 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

    摘要： A method for manufacturing a vertical transistor having a one side contact includes: forming separate active regions using trenches, on a semiconductor substrate, the active regions having first and second side surfaces facing the trenches; forming a first liner on the first and second side surfaces; forming a second liner which exposes a lower portion of the first liner on the first side surface; forming a third liner covering the portion of the first layer exposed by the second liner; forming a sacrifice layer on the third liner to fill the trench; forming an etch barrier to selectively expose upper end portions of the first to third liners positioned adjacent to the first side surface; selectively removing the third liner not covered by the etch barrier to expose a portion of the first liner not covered by the second liner; selectively removing the exposed portion of the first liner to expose a lower portion of the first side surface; and forming a buried bit line contacted with the exposed portion of the first side surface.

    摘要翻译： 一种用于制造具有一侧触点的垂直晶体管的方法包括：在半导体衬底上形成具有沟槽的分离的有源区，所述有源区具有面向沟槽的第一和第二侧表面; 在所述第一和第二侧表面上形成第一衬垫; 形成在所述第一侧表面上暴露所述第一衬垫的下部的第二衬垫; 形成覆盖由第二衬套暴露的第一层的部分的第三衬垫; 在第三衬垫上形成牺牲层以填充沟槽; 形成蚀刻阻挡层以选择性地暴露位于邻近第一侧表面的第一至第三衬垫的上端部分; 选择性地移除未被蚀刻阻挡层覆盖的第三衬垫，以暴露未被第二衬垫覆盖的第一衬垫的一部分; 选择性地去除所述第一衬里的暴露部分以暴露所述第一侧表面的下部; 以及形成与所述第一侧表面的暴露部分接触的掩埋位线。