公开(公告)号：US06965987B2

公开(公告)日：2005-11-15

申请号：US10713145

申请日：2003-11-17

申请人： Cheryl Senter Brashears ,  Johannes Wang ,  Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Cheryl Senter Brashears ,  Johannes Wang ,  Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/00 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38 ,  G06F9/34 ,  G06F9/44 ,  G06F12/04

CPC分类号： G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

公开(公告)号：US08019975B2

公开(公告)日：2011-09-13

申请号：US11113135

申请日：2005-04-25

申请人： Cheryl Senter Brashears ,  Johannes Wang ,  Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Cheryl Senter Brashears ,  Johannes Wang ,  Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

摘要翻译： 本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。 为了执行此任务，提供了一个加载存储单元，其主要目的是尽可能地使加载请求失效，以便尽可能快地将加载数据返回供指令执行单元使用。 如果没有地址冲突而没有写入，只能执行加载操作。 当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。 写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。 数据高速缓存单元返回8字节的未对齐数据。 加载/存储单元在返回指令执行单元之前将其正确对齐。 因此，加载存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

公开(公告)号：US06959375B2

公开(公告)日：2005-10-25

申请号：US10282045

申请日：2002-10-29

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/42 ,  G06F9/50 ,  G06F15/16

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果存储在临时数据寄存器中，直到执行所有先前的指令为止，从而按顺序退出执行的指令。

公开(公告)号：US06941447B2

公开(公告)日：2005-09-06

申请号：US10700520

申请日：2003-11-05

申请人： Le-Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le-Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/42 ,  G06F13/40

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

公开(公告)号：US5832292A

公开(公告)日：1998-11-03

申请号：US716728

申请日：1996-09-23

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F13/00

CPC分类号： G06F9/30167 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3885

摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

公开(公告)号：US5560032A

公开(公告)日：1996-09-24

申请号：US397016

申请日：1995-03-01

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program instruction sets. Each instruction set includes a plurality of fixed length instructions with a prescribed program order (in-order). The architecture also includes an instruction execution unit for dynamically examining the instruction sets and scheduling instructions for execution, including out-of-order execution, among a plurality of functional units. The data results of the executed instructions are concurrently distributed to a temporary buffer and a register file array and managed by associated control logic, including a register renaming unit, a dependency checker unit, done control unit, and retirement control unit. The architecture also optimizes the scheduling of data paths in accordance with the type of computational function, including integer, floating point, and boolean.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行和并发结果分配，可提高资源利用率和性能吞吐量。 计算机系统架构包括用于获取程序指令集的指令获取单元。 每个指令集包括具有规定程序顺序（按顺序）的多个固定长度指令。 该架构还包括用于在多个功能单元之间动态检查指令集和执行调度指令（包括无序执行）的指令执行单元。 所执行指令的数据结果同时分配给临时缓冲器和寄存器文件阵列，并由关联的控制逻辑管理，包括寄存器重命名单元，依赖检查单元，完成控制单元和退出控制单元。 该架构还根据计算函数的类型（包括整数，浮点和布尔值）优化数据路径的调度。

公开(公告)号：US07739482B2

公开(公告)日：2010-06-15

申请号：US11642599

申请日：2006-12-21

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F15/76

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

公开(公告)号：US07162610B2

公开(公告)日：2007-01-09

申请号：US10660671

申请日：2003-09-12

申请人： Le Trong Nguyen ,  Derek J Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H Trang

发明人： Le Trong Nguyen ,  Derek J Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H Trang

IPC分类号： G06F15/78 ,  G06F9/38 ,  G06F9/40

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

公开(公告)号：US06256720B1

公开(公告)日：2001-07-03

申请号：US09436986

申请日：1999-11-09

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F930

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

公开(公告)号：US6038653A

公开(公告)日：2000-03-14

申请号：US158568

申请日：1998-09-22

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3885

摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across mutliple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

摘要翻译： 高性能的基于RISC核心的微处理器架构包括用于从指令存储器取出指令集的指令获取单元和通过并行的功能单元阵列实现多个指令的并发执行的执行单元。 提取单元通常在指令缓冲器中保持预定数量的指令。 执行单元包括指令选择单元，耦合到指令缓冲器，用于选择用于执行的指令;以及多个功能单元，用于执行指令指定的功能操作。 在指令选择单元内的统一指令调度器，当确定可用于执行的指令并且实现必要的计算功能的功能单元中的至少一个可用时，通过功能单元启动对指令的处理。 在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要对数据执行的计算函数类型进行优化：整数，浮点和布尔值。 在每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。