公开(公告)号：US06590279B1

公开(公告)日：2003-07-08

申请号：US09470515

申请日：1999-12-22

申请人： Chieh-Ping Huang ,  Lian-Cherng Chiang ,  Wen-Ta Tsai

发明人： Chieh-Ping Huang ,  Lian-Cherng Chiang ,  Wen-Ta Tsai

IPC分类号： H01L2302

CPC分类号： H01L24/27 ,  H01L23/49513 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/85181 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package are proposed, which can help prevent the occurrence of cracking and delamination in the chips and the occurrence of voids in the encapsulant during the manufacture process. The dual-chip integrated circuit package is constructed on a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads. Further, the dual-chip integrated circuit package includes at least one support member attached to the front side of the first integrated circuit chip for providing a support to the bonding pads on the second integrated circuit chip; the support member being not smaller in dimension than the area where the bonding pads on the second integrated circuit chip are located. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the support members, and inner parts of the first and second leads of the leadframe. Since the support members can provide good support to the bonding pads on the second integrated circuit chip, it can help prevent the chips from being cracked during the manufacture process. The manufactured dual-chip integrated circuit package can be thus reliable in quality.

公开(公告)号：US06777266B2

公开(公告)日：2004-08-17

申请号：US10441778

申请日：2003-05-19

申请人： Chieh-Ping Huang ,  Lian-Cherng Chiang ,  Wen-Ta Tsai

发明人： Chieh-Ping Huang ,  Lian-Cherng Chiang ,  Wen-Ta Tsai

IPC分类号： H01L2160

CPC分类号： H01L24/27 ,  H01L23/49513 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/85181 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package are proposed, which can help prevent the occurrence of cracking and delamination in the chips and the occurrence of voids in the encapsulant during the manufacture process. The dual-chip integrated circuit package is constructed on a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads. Further, the dual-chip integrated circuit package includes at least one support member attached to the front side of the first integrated circuit chip for providing a support to the bonding pads on the second integrated circuit chip; the support member being not smaller in dimension than the area where the bonding pads on the second integrated circuit chip are located. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the support members, and inner parts of the first and second leads of the leadframe. Since the support members can provide good support to the bonding pads on the second integrated circuit chip, it can help prevent the chips from being cracked during the manufacture process. The manufactured dual-chip integrated circuit package can be thus reliable in quality.

摘要翻译： 提出了一种双芯片集成电路封装和制造这种双芯片集成电路封装的方法，可以帮助防止芯片中的开裂和分层的发生以及制造过程中密封剂中空隙的发生。 双芯片集成电路封装构造在具有多个第一引线和多个第二引线的引线框架上，以及在第一和第二引线之间的至少一对支撑构件。 此外，双芯片集成电路封装包括附接到第一集成电路芯片的前侧的至少一个支撑构件，用于向第二集成电路芯片上的焊盘提供支撑; 支撑构件的尺寸不小于第二集成电路芯片上的接合焊盘所在的区域。 密封剂用于封装第一集成电路芯片，第二集成电路芯片，支撑构件以及引线框架的第一引线和第二引线的内部部分。 由于支撑构件可以为第二集成电路芯片上的接合焊盘提供良好的支撑，所以可以帮助防止芯片在制造过程中破裂。 制造的双芯片集成电路封装的质量可靠可靠。

公开(公告)号：US06307257B1

公开(公告)日：2001-10-23

申请号：US09473310

申请日：1999-12-28

申请人： Chien-Ping Huang ,  Lian-Cherng Chiang ,  Wen-Ta Tsai

发明人： Chien-Ping Huang ,  Lian-Cherng Chiang ,  Wen-Ta Tsai

IPC分类号： H01L23495

CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A dual-chip integrated circuit (IC) package is provided, which is characterized in the use of a an extending portion formed from the leads of a leadframe to provide firm support to the bonding pads on the chips. The dual-chip integrated circuit package utilizes a leadframe having a first leads and a second leads, with a spacing being defined between the first and second leads; and the first leads is extended toward the spacing to form the extending portion at a downset position with respect to the second plane where the leadframe positions leads. A first integrated circuit chip is mounted on the extending portion in such a manner that the front side thereof is attached to the extending portion; and a second integrated circuit chip is attached to the first integrated circuit chip in a back-to-back manner. The bonding pads on the two integrated circuit chips are electrically connected to the first and second leads via a plurality of bonding wires. The use of the extending portion for the attachment of the two integrated circuit chips can help prevent delamination of the chips and can provide firm support to the bonding pads on the chips so that the chips can be prevented from being cracked during the wire-bonding process. The manufactured integrated circuit package can therefore be more assured in reliability and quality.

摘要翻译： 提供了一种双芯片集成电路（IC）封装，其特征在于使用由引线框的引线形成的延伸部分，为芯片上的焊盘提供坚固的支撑。 双芯片集成电路封装采用具有第一引线和第二引线的引线框架，间隔限定在第一和第二引线之间; 并且第一引线朝向间隔延伸，以在相对于引线框架位置引导的第二平面处于下降位置处形成延伸部分。 第一集成电路芯片以其前侧附接到延伸部分的方式安装在延伸部分上; 并且第二集成电路芯片以背靠背的方式附接到第一集成电路芯片。 两个集成电路芯片上的接合焊盘经由多根接合线电连接到第一和第二引线。 使用用于连接两个集成电路芯片的延伸部分可以帮助防止芯片的分层，并且可以为芯片上的焊盘提供牢固的支撑，使得可以防止芯片在引线接合过程中被破裂 。 因此，制造的集成电路封装在可靠性和质量方面可以更加确保。

公开(公告)号：USD537283S1

公开(公告)日：2007-02-27

申请号：US29241370

申请日：2005-10-26

申请人： Wen-Ta Tsai

设计人： Wen-Ta Tsai

公开(公告)号：US5496593A

公开(公告)日：1996-03-05

申请号：US333037

申请日：1994-11-01

申请人： Wen-Ta Tsai ,  Chong-Cheng Huang ,  Ju-Tung Lee

发明人： Wen-Ta Tsai ,  Chong-Cheng Huang ,  Ju-Tung Lee

IPC分类号： C23C24/10 ,  C23C26/02 ,  B05D3/06

CPC分类号： C23C26/02 ,  C23C24/103

摘要： A process for producing a nitrogen-alloyed stainless steel layer on steel by applying nitride containing mixed metal powder or stainless powder to the steel surface, and thereafter treating the steel with laser beams.

摘要翻译： 一种通过在钢表面上涂覆含有混合金属粉末或不锈钢粉末的氮化物，然后用激光束处理钢来制造氮合金不锈钢层的方法。

公开(公告)号：US06903441B2

公开(公告)日：2005-06-07

申请号：US10452566

申请日：2003-05-30

申请人： Chin Fa Wang ,  Wen-Ta Tsai ,  Yuan-Ping Joe

发明人： Chin Fa Wang ,  Wen-Ta Tsai ,  Yuan-Ping Joe

IPC分类号： H01L21/60 ,  H01L23/48 ,  H01L23/50 ,  H01L23/498 ,  H01L21/58

CPC分类号： H01L23/50 ,  H01L23/481 ,  H01L24/27 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10157 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor package and a fabrication method thereof are provided, in which a ground pad on a chip is electrically connected to a ground plane on a substrate by means of an electrically-conductive wall formed over a side surface of the chip and an electrically-conductive adhesive used for attaching the chip to the substrate. Therefore, a wire-bonding process is merely implemented for power pads and signal I/O (input/output) pads on the chip without having to form ground wires on the ground pads for electrical connection purposes. This benefit allows the use of a reduced number of bonding wires and simplifies wire arrangement or routability. And, a grounding path from the chip through the electrically-conductive wall and electrically-conductive adhesive to the substrate is shorter than the conventional one of using ground wires, thereby reducing a ground-bouncing effect and improving electrical performances of the semiconductor package.

摘要翻译： 提供一种半导体封装及其制造方法，其中芯片上的接地焊盘通过形成在芯片的侧表面上的导电壁电连接到基板上的接地平面，并且导电 用于将芯片附接到基板的粘合剂。 因此，仅针对芯片上的电源焊盘和信号I / O（输入/输出）焊盘实现引线接合工艺，而不必在接地焊盘上形成用于电连接目的的接地线。 这种优点允许使用减少数量的接合线并简化线布置或可布线性。 并且，从芯片通过导电壁和导电粘合剂到衬底的接地路径比使用接地线的传统接地线的接地路径短，从而降低了接地跳动效应并提高了半导体封装的电性能。

公开(公告)号：USD476495S1

公开(公告)日：2003-07-01

申请号：US29156456

申请日：2002-02-27

申请人： Wen-Ta Tsai

设计人： Wen-Ta Tsai

公开(公告)号：US5411770A

公开(公告)日：1995-05-02

申请号：US266046

申请日：1994-06-27

申请人： Wen-Ta Tsai ,  Ju-Tung Lee ,  Tai-Hwang Lai

发明人： Wen-Ta Tsai ,  Ju-Tung Lee ,  Tai-Hwang Lai

IPC分类号： C23C10/18 ,  C23C26/02 ,  C23C24/10

CPC分类号： C23C10/18 ,  C23C26/02

摘要： The surface of stainless steel can be hardened by coating a silicon nitride gel and then scanning by CO.sub.2 laser to form a surface alloy layer thereon. The thickness and hardness of the surface alloy layer are both uniform. The Vicker's hardness of the layer can be as high as 1200 Hv. This method can be operated in a common atmosphere or nitride atmosphere at normal pressure, therefore it is more economic than ion nitriding or plasma nitriding.

摘要翻译： 不锈钢表面可以通过涂覆氮化硅凝胶硬化，然后用CO 2激光扫描，在其上形成表面合金层。 表面合金层的厚度和硬度均匀。 Vicker的硬度可以高达1200 Hv。 该方法可以在普通气氛或常压氮化气氛下运行，因此比离子氮化或等离子体氮化更经济。

公开(公告)号：USD538075S1

公开(公告)日：2007-03-13

申请号：US29241368

申请日：2005-10-26

申请人： Wen-Ta Tsai

设计人： Wen-Ta Tsai

公开(公告)号：USD512574S1

公开(公告)日：2005-12-13

申请号：US29203821

申请日：2004-04-20

申请人： Wen-Ta Tsai

设计人： Wen-Ta Tsai