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13 条记录 (耗时 0.032 秒)

    Low temperature method for metal deposition
    1.
    发明授权
    Low temperature method for metal deposition 有权
    金属沉积低温法

    公开(公告)号：US07176081B2

    公开(公告)日：2007-02-13

    申请号：US10851044

    申请日：2004-05-20

    申请人： Chih-Fu Chang ,  Yen-Hsiu Chen ,  Hung-Jen Lin ,  Ming-Chu King ,  Ching-Hwanq Su ,  Chih-Mu Huang ,  Yun Chang

    发明人： Chih-Fu Chang ,  Yen-Hsiu Chen ,  Hung-Jen Lin ,  Ming-Chu King ,  Ching-Hwanq Su ,  Chih-Mu Huang ,  Yun Chang

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/2855 ,  H01L21/32051 ,  H01L28/60

    摘要： A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.

    摘要翻译： 公开了一种适用于在金属 - 绝缘体 - 金属（MIM）电容器的制造中在基底上沉积金属膜的新颖的低温金属沉积方法。 该方法包括使用小于一般约270℃的沉积温度在基板上沉积金属膜。所得到的金属膜的特征在于增强的厚度均匀性和减小的晶粒聚集，否则倾向于降低电容器或其它的操作完整性 金属膜是其一部分的装置。 此外，金属膜的特征在于本征击穿电压（V BAT）改善。

    Integrated circuit structure and method of forming the same
    3.
    发明授权
    Integrated circuit structure and method of forming the same 有权
    集成电路结构及其形成方法

    公开(公告)号：US08736015B2

    公开(公告)日：2014-05-27

    申请号：US13246495

    申请日：2011-09-27

    申请人： Yao-Jen Tsai ,  Chih-Fu Chang ,  Chih-Kang Chuang ,  Yee-Ren Wuang ,  David Yen ,  Yuan-Jen Liao ,  Shih-Che Fang ,  Hung-Che Hsueh ,  Chih Mou Huang

    发明人： Yao-Jen Tsai ,  Chih-Fu Chang ,  Chih-Kang Chuang ,  Yee-Ren Wuang ,  David Yen ,  Yuan-Jen Liao ,  Shih-Che Fang ,  Hung-Che Hsueh ,  Chih Mou Huang

    IPC分类号： H01L29/06

    CPC分类号： H01L27/0251

    摘要： An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path.

    摘要翻译： 一个实施例是集成电路（IC）结构。 该结构包括衬底中的深n阱，深n阱中的第一拾取装置，深n阱中的第一信号装置，衬底中的耗散装置，衬底中的第二信号装置，第一电路 在第一拾取装置和耗散装置之间，以及在第一信号装置和第二信号装置之间的第二电路径。 耗散装置在深n井外，第二信号装置在深n井外。 第一电路的最高点低于第二电路的最高点。

    Reliability assessment of capacitor device
    4.
    发明授权
    Reliability assessment of capacitor device 有权
    电容器件的可靠性评估

    公开(公告)号：US09310425B2

    公开(公告)日：2016-04-12

    申请号：US13175263

    申请日：2011-07-01

    申请人： Huang Jiun-Jie ,  Chi-Yen Lin ,  Ling-Sung Wang ,  Chih-Fu Chang

    发明人： Huang Jiun-Jie ,  Chi-Yen Lin ,  Ling-Sung Wang ,  Chih-Fu Chang

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2856

    摘要： A method of reliability testing of a semiconductor device is described. The embodiment, includes providing a capacitor including an insulating layer interposing two conductive layers. A plurality of voltages are provided to the capacitor including providing a first voltage and a second voltage greater than the first voltage. A leakage associated with the capacitor is measured while applying the second voltage. In an embodiment, the leakage measured while applying the second voltage indicates that a failure of the insulating layer of the capacitor has occurred. In an embodiment, the capacitor is an inter-digitated metal-oxide-metal (MOM) capacitor. The reliability testing may be correlated to TDDB test results. The reliability testing may be performed at a wafer-level.

    摘要翻译： 描述了半导体器件的可靠性测试方法。 该实施例包括提供包括插入两个导电层的绝缘层的电容器。 向电容器提供多个电压，包括提供大于第一电压的第一电压和第二电压。 在施加第二电压的同时测量与电容器相关的泄漏。 在一个实施例中，在施加第二电压时测量的泄漏表明电容器的绝缘层发生故障。 在一个实施例中，电容器是数字化的金属氧化物金属（MOM）电容器。 可靠性测试可能与TDDB测试结果相关。 可以在晶片级进行可靠性测试。

    Spring-forming control system and its control method for a spring forming machine
    5.
    发明申请
    Spring-forming control system and its control method for a spring forming machine 有权
    弹簧成形控制系统及其弹簧成型机的控制方法

    公开(公告)号：US20080270927A1

    公开(公告)日：2008-10-30

    申请号：US11899821

    申请日：2007-09-07

    申请人： Chih-Fu Chang

    发明人： Chih-Fu Chang

    IPC分类号： G06F3/048 ,  G06F19/00

    CPC分类号： G05B19/4093 ,  B21F35/00 ,  G05B2219/36252 ,  G05B2219/36253 ,  Y02P90/265 ,  Y10T29/49607 ,  Y10T29/49609

    摘要： A spring-forming control system and its control method for a spring forming machine in which the spring-forming control system uses a host computer to provide graphical spring parameter setting, program modification, and dragline-method program modification graphical interfaces that are selectively switchable on a display monitor. After setting of spring processing parameters through the spring parameter setting interface, a trial production is done subject to a spring parameter auto-generation software built in the spring-forming control system, and then the production is started if the trial meets the requirements, or the spring processing parameters are modified through the spring parameter setting interface, program modification interface, or dragline-method program modification interface if the trial does not meet the requirements, and then a further trial production is performed till the shaped spring meets the requirements. A spring preview is available during running of the spring-forming control system. The graphic interface operation has the advantages of convenience, rapidness, and accuracy.

    摘要翻译： 一种弹簧成形控制系统及其控制方法，其中弹簧成形控制系统使用主计算机提供图形弹簧参数设置，程序修改和可选择切换的程序修改图形界面 显示监视器。 通过弹簧参数设置界面设置弹簧加工参数后，根据弹簧成形控制系统内置的弹簧参数自动生成软件进行试生产，然后如果试验符合要求，则开始生产，或 如果试验不符合要求，弹簧加工参数通过弹簧参数设置界面，程序修改界面或拉拔方式程序修改界面进行修改，然后进行进一步的试制，直到成形弹簧满足要求。 在弹簧成型控制系统的运行过程中可以使用弹簧预览。 图形界面操作具有方便，快捷，准确的优点。

    Dopant implantation method using multi-step implants
    6.
    发明授权
    Dopant implantation method using multi-step implants 有权
    使用多步植入物的掺杂剂植入法

    公开(公告)号：US08008158B2

    公开(公告)日：2011-08-30

    申请号：US12170656

    申请日：2008-07-10

    申请人： Tse-En Chang ,  Chih-Fu Chang ,  Bone-Fong Wu ,  Chieh Chih Ting ,  Shao Hua Wang ,  Pu-Fang Chen ,  Yen Chuang

    发明人： Tse-En Chang ,  Chih-Fu Chang ,  Bone-Fong Wu ,  Chieh Chih Ting ,  Shao Hua Wang ,  Pu-Fang Chen ,  Yen Chuang

    IPC分类号： H01L21/336 ,  H01L21/8236

    CPC分类号： H01L21/26513 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration.

    摘要翻译： 在具有目标掺杂剂浓度的掺杂剂分布的MOS晶体管器件中形成掺杂剂注入区域的方法包括：将第一浓度的掺杂剂注入到衬底的区域中，其中掺杂剂的第一浓度小于目标掺杂剂浓度， 并且在植入步骤之后不退火衬底，执行至少一个第二注入步骤以将至少一个第二浓度的掺杂剂注入到衬底的区域中，以使该区域中的掺杂剂浓度达到目标掺杂剂浓度。

    RELIABILITY ASSESSMENT OF CAPACITOR DEVICE
    7.
    发明申请
    RELIABILITY ASSESSMENT OF CAPACITOR DEVICE 有权
    电容器的可靠性评估

    公开(公告)号：US20130002263A1

    公开(公告)日：2013-01-03

    申请号：US13175263

    申请日：2011-07-01

    申请人： Huang Jiun-Jie ,  Chi-Yen Lin ,  Ling-Sung Wang ,  Chih-Fu Chang

    发明人： Huang Jiun-Jie ,  Chi-Yen Lin ,  Ling-Sung Wang ,  Chih-Fu Chang

    IPC分类号： G01R31/12

    CPC分类号： G01R31/2856

    摘要： A method of reliability testing of a semiconductor device is described. The embodiment, includes providing a capacitor including an insulating layer interposing two conductive layers. A plurality of voltages are provided to the capacitor including providing a first voltage and a second voltage greater than the first voltage. A leakage associated with the capacitor is measured while applying the second voltage. In an embodiment, the leakage measured while applying the second voltage indicates that a failure of the insulating layer of the capacitor has occurred. In an embodiment, the capacitor is an inter-digitated metal-oxide-metal (MOM) capacitor. The reliability testing may be correlated to TDDB test results. The reliability testing may be performed at a wafer-level.

    摘要翻译： 描述了半导体器件的可靠性测试方法。 该实施例包括提供包括插入两个导电层的绝缘层的电容器。 向电容器提供多个电压，包括提供大于第一电压的第一电压和第二电压。 在施加第二电压的同时测量与电容器相关的泄漏。 在一个实施例中，在施加第二电压时测量的泄漏表明电容器的绝缘层发生故障。 在一个实施例中，电容器是数字化的金属氧化物金属（MOM）电容器。 可靠性测试可能与TDDB测试结果相关。 可以在晶片级进行可靠性测试。

    Spring-forming control system and its control method for a spring forming machine
    8.
    发明授权
    Spring-forming control system and its control method for a spring forming machine 有权
    弹簧成形控制系统及其弹簧成型机的控制方法

    公开(公告)号：US07676297B2

    公开(公告)日：2010-03-09

    申请号：US11899821

    申请日：2007-09-07

    申请人： Chih-Fu Chang

    发明人： Chih-Fu Chang

    IPC分类号： G06F19/00 ,  B23P13/00 ,  B21F3/02 ,  B21F3/10 ,  B21C47/00

    CPC分类号： G05B19/4093 ,  B21F35/00 ,  G05B2219/36252 ,  G05B2219/36253 ,  Y02P90/265 ,  Y10T29/49607 ,  Y10T29/49609

    摘要： A spring-forming control system and its control method for a spring forming machine in which the spring-forming control system uses a host computer to provide graphical spring parameter setting, program modification, and dragline-method program modification graphical interfaces that are selectively switchable on a display monitor. After setting of spring processing parameters through the spring parameter setting interface, a trial production is done subject to a spring parameter auto-generation software built in the spring-forming control system, and then the production is started if the trial meets the requirements, or the spring processing parameters are modified through the spring parameter setting interface, program modification interface, or dragline-method program modification interface if the trial does not meet the requirements, and then a further trial production is performed till the shaped spring meets the requirements. A spring preview is available during running of the spring-forming control system. The graphic interface operation has the advantages of convenience, rapidness, and accuracy.

    摘要翻译： 一种弹簧成形控制系统及其控制方法，其中弹簧成形控制系统使用主计算机提供图形弹簧参数设置，程序修改和可选择切换的程序修改图形界面 显示监视器。 通过弹簧参数设置界面设置弹簧加工参数后，根据弹簧成形控制系统内置的弹簧参数自动生成软件进行试生产，然后如果试验符合要求，则开始生产，或 如果试验不符合要求，弹簧加工参数通过弹簧参数设置界面，程序修改界面或拉拔方式程序修改界面进行修改，然后进行进一步的试制，直到成形弹簧满足要求。 在弹簧成型控制系统的运行过程中可以使用弹簧预览。 图形界面操作具有方便，快捷，准确的优点。

    Integrated Circuit Structure and Method of Forming the Same
    10.
    发明申请
    Integrated Circuit Structure and Method of Forming the Same 有权
    集成电路结构及其形成方法

    公开(公告)号：US20130075856A1

    公开(公告)日：2013-03-28

    申请号：US13246495

    申请日：2011-09-27

    申请人： Yao-Jen Tsai ,  Chih-Fu Chang ,  Chih-Kang Chuang ,  Yee-Ren Wuang ,  David Yen ,  Yuan-Jen Liao ,  Shih-Che Fang ,  Hung-Che Hsueh ,  Chih Mou Huang

    发明人： Yao-Jen Tsai ,  Chih-Fu Chang ,  Chih-Kang Chuang ,  Yee-Ren Wuang ,  David Yen ,  Yuan-Jen Liao ,  Shih-Che Fang ,  Hung-Che Hsueh ,  Chih Mou Huang

    IPC分类号： H01L29/06

    CPC分类号： H01L27/0251

    摘要： An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path.

    摘要翻译： 一个实施例是集成电路（IC）结构。 该结构包括衬底中的深n阱，深n阱中的第一拾取装置，深n阱中的第一信号装置，衬底中的耗散装置，衬底中的第二信号装置，第一电路 在第一拾取装置和耗散装置之间，以及在第一信号装置和第二信号装置之间的第二电路径。 耗散装置在深n井外，第二信号装置在深n井外。 第一电路的最高点低于第二电路的最高点。