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    Shallow trench isolation
    1.
    发明授权
    Shallow trench isolation 有权
    浅沟隔离

    公开(公告)号：US07998815B2

    公开(公告)日：2011-08-16

    申请号：US12192626

    申请日：2008-08-15

    申请人： Xia Li ,  Ming-Chu King

    发明人： Xia Li ,  Ming-Chu King

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76232

    摘要： Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a high-temperature anneal of the silicon substrate to form a buried oxide layer. The method also includes performing an etch to deepen the narrow trench to reach the buried oxide layer. The method further includes depositing a filling material to form a top filling layer in the narrow trench.

    摘要翻译： 公开了浅沟槽隔离方法。 在特定实施例中，一种方法包括在硅衬底的窄沟槽的底表面下注入氧气，并执行硅衬底的高温退火以形成掩埋氧化物层。 该方法还包括执行蚀刻以加深窄沟槽以到达掩埋氧化物层。 该方法还包括沉积填充材料以在窄沟槽中形成顶部填充层。

    Structure of a mask for use in a lithography process of a semiconductor fabrication
    2.
    发明授权
    Structure of a mask for use in a lithography process of a semiconductor fabrication 失效
    用于半导体制造的光刻工艺中的掩模的结构

    公开(公告)号：US5798192A

    公开(公告)日：1998-08-25

    申请号：US834330

    申请日：1997-04-15

    申请人： Ming-Chu King ,  Shih-Shiung Chen ,  Ying-Chen Chao

    发明人： Ming-Chu King ,  Shih-Shiung Chen ,  Ying-Chen Chao

    IPC分类号： G03F1/00 ,  G03F9/00

    CPC分类号： G03F1/40 ,  G03F1/50

    摘要： A structure of a mask for use in a lithography process in a semiconductor fabrication procedure is disclosed. The structure comprising: a mask base being made of transparent material; a plurality of patterns formed on said mask base, said patterns being used for generating an image on a wafer and being made of a conductive opaque material; and a conductive layer formed on said mask base and said plurality of patterns.

    摘要翻译： 公开了一种用于半导体制造过程中的光刻工艺中的掩模的结构。 该结构包括：掩模基底，由透明材料制成; 形成在所述掩模基底上的多个图案，所述图案用于在晶片上产生图像并由导电不透明材料制成; 以及形成在所述掩模基底和所述多个图案上的导电层。

    METAL-OXIDE-METAL STRUCTURE WITH IMPROVED CAPACITIVE COUPLING AREA
    3.
    发明申请
    METAL-OXIDE-METAL STRUCTURE WITH IMPROVED CAPACITIVE COUPLING AREA 有权
    金属氧化物金属结构与改进的电容耦合区域

    公开(公告)号：US20100123214A1

    公开(公告)日：2010-05-20

    申请号：US12274255

    申请日：2008-11-19

    申请人： CHAO-CHI CHEN ,  Ming-Chu King ,  Chen Cheng Chou

    发明人： CHAO-CHI CHEN ,  Ming-Chu King ,  Chen Cheng Chou

    IPC分类号： H01L29/92 ,  H01G4/005

    CPC分类号： H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.

    摘要翻译： 一种堆叠的金属氧化物金属（MOM）电容器结构及其形成方法，以增加电极/电容器介质耦合面积以增加电容，所述MOM电容器结构包括堆叠关系的多个金属化层; 其中每个金属化层包括具有第一中间电容器电介质的基本上平行的隔开的导电电极线部分; 并且其中所述导电电极线部分通过形成在第二电容器电介质中并设置在所述导电电极线部分下方的导电镶嵌线部分在金属化层之间电互连。

    Metal-oxide-metal structure with improved capacitive coupling area
    4.
    发明授权
    Metal-oxide-metal structure with improved capacitive coupling area 有权
    具有改善电容耦合面积的金属氧化物 - 金属结构

    公开(公告)号：US08207567B2

    公开(公告)日：2012-06-26

    申请号：US12274255

    申请日：2008-11-19

    申请人： Chao-Chi Chin ,  Ming-Chu King ,  Chen Cheng Chou

    发明人： Chao-Chi Chin ,  Ming-Chu King ,  Chen Cheng Chou

    IPC分类号： H01L29/92

    CPC分类号： H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.

    摘要翻译： 一种堆叠的金属氧化物金属（MOM）电容器结构及其形成方法，以增加电极/电容器介质耦合面积以增加电容，所述MOM电容器结构包括堆叠关系的多个金属化层; 其中每个金属化层包括具有第一中间电容器电介质的基本上平行的隔开的导电电极线部分; 并且其中所述导电电极线部分通过形成在第二电容器电介质中并设置在所述导电电极线部分下方的导电镶嵌线部分在金属化层之间电互连。

    Method of forming conductor shielding to prevent arcing effect during contact implant process
    5.
    发明授权
    Method of forming conductor shielding to prevent arcing effect during contact implant process 有权
    在接触植入过程中形成导体屏蔽以防止电弧效应的方法

    公开(公告)号：US6069074A

    公开(公告)日：2000-05-30

    申请号：US236490

    申请日：1999-01-25

    申请人： Chiang Fu ,  Jun-Yen Huang ,  Ming Chu King ,  Chien-Chen Chen

    发明人： Chiang Fu ,  Jun-Yen Huang ,  Ming Chu King ,  Chien-Chen Chen

    IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76859 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/28512 ,  H01L21/76843

    摘要： A method preventing the arcing effect during contact implantation by employing a conductive shielding film within the contact opening in the fabrication of an integrated circuit is described. A dielectric layer is provided overlying a semiconductor substrate of a wafer. The dielectric layer is etched into to provide a contact opening through the dielectric layer to the semiconductor substrate. A conducting layer is deposited overlying the dielectric layer and within the contact opening. A photoresist mask is formed over the conducting layer having an opening above the contact opening. The wafer is placed in an ion implantation chamber wherein the wafer is held by means of an electrostatic chuck. Ions are implanted into the semiconductor substrate through the conducting layer not covered by the photoresist mask wherein some of the ions are trapped on photoresist mask and wherein the conducting layer conducts the trapped ions throughout the wafer thereby preventing charge damage to the dielectric layer.

    摘要翻译： 描述了在集成电路的制造中通过在接触开口内采用导电屏蔽膜来防止接触注入期间的电弧效应的方法。 提供覆盖在晶片的半导体衬底上的电介质层。 蚀刻介电层以提供通过介电层到半导体衬底的接触开口。 导电层沉积在电介质层上并在接触开口内。 在具有在接触开口上方的开口的导电层上形成光致抗蚀剂掩模。 将晶片放置在离子注入室中，其中晶片通过静电卡盘保持。 离子通过未被光致抗蚀剂掩模覆盖的导电层注入到半导体衬底中，其中一些离子被捕获在光致抗蚀剂掩模上，并且其中导电层导致截留在晶片上的被俘获的离子，从而防止对电介质层的电荷损伤。

    Shallow Trench Isolation
    7.
    发明申请
    Shallow Trench Isolation 有权
    浅沟槽隔离

    公开(公告)号：US20100038744A1

    公开(公告)日：2010-02-18

    申请号：US12192626

    申请日：2008-08-15

    申请人： Xia Li ,  Ming-Chu King

    发明人： Xia Li ,  Ming-Chu King

    IPC分类号： H01L21/762 ,  H01L23/58

    CPC分类号： H01L21/76232

    摘要： Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a high-temperature anneal of the silicon substrate to form a buried oxide layer. The method also includes performing an etch to deepen the narrow trench to reach the buried oxide layer. The method further includes depositing a filling material to form a top filling layer in the narrow trench.

    摘要翻译： 公开了浅沟槽隔离方法。 在特定实施例中，一种方法包括在硅衬底的窄沟槽的底表面下注入氧气，并执行硅衬底的高温退火以形成掩埋氧化物层。 该方法还包括执行蚀刻以加深窄沟槽以到达掩埋氧化物层。 该方法还包括沉积填充材料以在窄沟槽中形成顶部填充层。

    Low temperature method for metal deposition
    8.
    发明授权
    Low temperature method for metal deposition 有权
    金属沉积低温法

    公开(公告)号：US07176081B2

    公开(公告)日：2007-02-13

    申请号：US10851044

    申请日：2004-05-20

    申请人： Chih-Fu Chang ,  Yen-Hsiu Chen ,  Hung-Jen Lin ,  Ming-Chu King ,  Ching-Hwanq Su ,  Chih-Mu Huang ,  Yun Chang

    发明人： Chih-Fu Chang ,  Yen-Hsiu Chen ,  Hung-Jen Lin ,  Ming-Chu King ,  Ching-Hwanq Su ,  Chih-Mu Huang ,  Yun Chang

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/2855 ,  H01L21/32051 ,  H01L28/60

    摘要： A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.

    摘要翻译： 公开了一种适用于在金属 - 绝缘体 - 金属（MIM）电容器的制造中在基底上沉积金属膜的新颖的低温金属沉积方法。 该方法包括使用小于一般约270℃的沉积温度在基板上沉积金属膜。所得到的金属膜的特征在于增强的厚度均匀性和减小的晶粒聚集，否则倾向于降低电容器或其它的操作完整性 金属膜是其一部分的装置。 此外，金属膜的特征在于本征击穿电压（V BAT）改善。

    Apparatus for identification of locations of a circuit within an integrated circuit having low speed performance
    10.
    发明授权
    Apparatus for identification of locations of a circuit within an integrated circuit having low speed performance 有权
    用于识别具有低速性能的集成电路内的电路的位置的装置

    公开(公告)号：US07208934B2

    公开(公告)日：2007-04-24

    申请号：US10761903

    申请日：2004-01-21

    申请人： Ming-Chu King ,  Chia-Wen Shiue

    发明人： Ming-Chu King ,  Chia-Wen Shiue

    IPC分类号： G01R23/02

    CPC分类号： G01R31/31727

    摘要： A test circuit for identification of locations with low speed performance. A grid of ring oscillator units and switches connect or disconnect the ring oscillator units to or from each other, such that the locations with low speed performance are identified according to frequencies of oscillation signals generated by rows and columns of ring oscillators respectively formed by operating the test circuit in two different modes.

    摘要翻译： 用于识别低速性能位置的测试电路。 环形振荡器单元和开关的网格将环形振荡器单元彼此连接或断开，使得具有低速性能的位置根据由分别由操作的振荡器的行和列产生的振荡信号的频率来识别 测试电路有两种不同的模式。