公开(公告)号：US08987033B2

公开(公告)日：2015-03-24

申请号：US13196560

申请日：2011-08-02

申请人： Ching-Chung Su ,  Shih-Chang Liu ,  Shih Pei Chou ,  Chia-Shiung Tsai ,  Chun-Tsung Kuo ,  Wen-I Hsu ,  Yi-Shin Chu

发明人： Ching-Chung Su ,  Shih-Chang Liu ,  Shih Pei Chou ,  Chia-Shiung Tsai ,  Chun-Tsung Kuo ,  Wen-I Hsu ,  Yi-Shin Chu

IPC分类号： H01L21/00 ,  H01L27/146

CPC分类号： H01L27/1463

摘要： A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed.

摘要翻译： 一种方法包括在衬底上形成阻挡层，并蚀刻阻挡层以在阻挡层中形成沟槽。 形成介电层，其中电介质层包括阻挡层上的第一部分和沟槽中的第二部分。 在形成介电层的步骤之后，进行注入以将杂质注入衬底以形成深阱区。 在植入之后，去除介电层和阻挡层。

公开(公告)号：US20130034929A1

公开(公告)日：2013-02-07

申请号：US13196560

申请日：2011-08-02

申请人： Ching-Chung Su ,  Shih-Chang Liu ,  Shih Pei Chou ,  Chia-Shiung Tsai ,  Chun-Tsung Kuo ,  Wen-I Hsu ,  Yi-Shin Chu

发明人： Ching-Chung Su ,  Shih-Chang Liu ,  Shih Pei Chou ,  Chia-Shiung Tsai ,  Chun-Tsung Kuo ,  Wen-I Hsu ,  Yi-Shin Chu

IPC分类号： H01L31/18

CPC分类号： H01L27/1463

摘要： A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed.

摘要翻译： 一种方法包括在衬底上形成阻挡层，并蚀刻阻挡层以在阻挡层中形成沟槽。 形成介电层，其中电介质层包括阻挡层上的第一部分和沟槽中的第二部分。 在形成介电层的步骤之后，进行注入以将杂质注入衬底以形成深阱区。 在植入之后，去除介电层和阻挡层。

公开(公告)号：US08610227B2

公开(公告)日：2013-12-17

申请号：US12903871

申请日：2010-10-13

申请人： Shih Pei Chou ,  Shih-Chang Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

发明人： Shih Pei Chou ,  Shih-Chang Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L31/0232

CPC分类号： H01L27/14627 ,  H01L27/14621 ,  H01L27/14685

摘要： Provided is an image sensor device. The image sensor device includes a pixel formed in a substrate. The image sensor device includes a first micro-lens embedded in a transparent layer over the substrate. The first micro-lens has a first upper surface that has an angular tip. The image sensor device includes a color filter that is located over the transparent layer. The image sensor device includes a second micro-lens that is formed over the color filter. The second micro-lens has a second upper surface that has an approximately rounded profile. The pixel, the first micro-lens, the color filter, and the second micro-lens are all at least partially aligned with one another in a vertical direction.

摘要翻译： 提供了一种图像传感器装置。 图像传感器装置包括形成在基板中的像素。 图像传感器装置包括嵌入在基板上的透明层中的第一微透镜。 第一微透镜具有具有角尖的第一上表面。 图像传感器装置包括位于透明层上方的滤色器。 图像传感器装置包括形成在滤色器上的第二微透镜。 第二微透镜具有第二上表面，其具有近似圆形的轮廓。 像素，第一微透镜，滤色器和第二微透镜在垂直方向上至少部分地彼此对准。

公开(公告)号：US20120091549A1

公开(公告)日：2012-04-19

申请号：US12903871

申请日：2010-10-13

申请人： Shih Pei Chou ,  Shih-Chang Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

发明人： Shih Pei Chou ,  Shih-Chang Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L31/0232 ,  H01L31/18

CPC分类号： H01L27/14627 ,  H01L27/14621 ,  H01L27/14685

摘要： Provided is an image sensor device. The image sensor device includes a pixel formed in a substrate. The image sensor device includes a first micro-lens embedded in a transparent layer over the substrate. The first micro-lens has a first upper surface that has an angular tip. The image sensor device includes a color filter that is located over the transparent layer. The image sensor device includes a second micro-lens that is formed over the color filter. The second micro-lens has a second upper surface that has an approximately rounded profile. The pixel, the first micro-lens, the color filter, and the second micro-lens are all at least partially aligned with one another in a vertical direction.

摘要翻译： 提供了一种图像传感器装置。 图像传感器装置包括形成在基板中的像素。 图像传感器装置包括嵌入在基板上的透明层中的第一微透镜。 第一微透镜具有具有角尖的第一上表面。 图像传感器装置包括位于透明层上方的滤色器。 图像传感器装置包括形成在滤色器上的第二微透镜。 第二微透镜具有第二上表面，其具有近似圆形的轮廓。 像素，第一微透镜，滤色器和第二微透镜在垂直方向上至少部分地彼此对准。

公开(公告)号：US20120056305A1

公开(公告)日：2012-03-08

申请号：US12874362

申请日：2010-09-02

申请人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/66287 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7378

摘要： The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

摘要翻译： 本公开提供了一种双极结型晶体管（BJT）器件和用于制造BJT器件的方法。 在一个实施例中，BJT器件包括：具有集电极区域和设置在半导体层上的材料层的半导体衬底。 材料层在其中具有暴露出集电极区域的一部分的沟槽。 基底结构，间隔物和发射体结构设置在材料层的沟槽内。 每个间隔物具有顶部宽度和底部宽度，顶部宽度基本上等于底部宽度。

公开(公告)号：US08501572B2

公开(公告)日：2013-08-06

申请号：US12874362

申请日：2010-09-02

申请人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/66287 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7378

摘要： The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

摘要翻译： 本公开提供了一种双极结型晶体管（BJT）器件和用于制造BJT器件的方法。 在一个实施例中，BJT器件包括：具有集电极区域和设置在半导体层上的材料层的半导体衬底。 材料层在其中具有暴露出集电极区域的一部分的沟槽。 基底结构，间隔物和发射体结构设置在材料层的沟槽内。 每个间隔物具有顶部宽度和底部宽度，顶部宽度基本上等于底部宽度。

公开(公告)号：US08227850B2

公开(公告)日：2012-07-24

申请号：US12723381

申请日：2010-03-12

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L29/76

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

公开(公告)号：US20100171167A1

公开(公告)日：2010-07-08

申请号：US12723381

申请日：2010-03-12

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

公开(公告)号：US07700473B2

公开(公告)日：2010-04-20

申请号：US11784633

申请日：2007-04-09

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧上的尺寸上横向减小以产生底切。

公开(公告)号：US20080248620A1

公开(公告)日：2008-10-09

申请号：US11784633

申请日：2007-04-09

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。