公开(公告)号：US20240120281A1

公开(公告)日：2024-04-11

申请号：US18524118

申请日：2023-11-30

Applicant: Ping-Jung Yang

Inventor： Ping-Jung Yang

IPC: H01L23/538 ,  H01L23/15 ,  H01L23/498 ,  H10K77/10

CPC classification number: H01L23/5384 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H10K77/10 ,  H01L24/13 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/181

Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.

公开(公告)号：US11935866B2

公开(公告)日：2024-03-19

申请号：US16936112

申请日：2020-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/00 ,  B23K1/00 ,  B23K101/42 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L24/83 ,  B23K1/0016 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  B23K2101/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3841 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2224/13116 ,  H01L2924/014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/014 ,  H01L2224/13155 ,  H01L2924/014 ,  H01L2224/13113 ,  H01L2924/014 ,  H01L2224/1147 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2224/05027 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/05186 ,  H01L2924/04953 ,  H01L2224/1146 ,  H01L2924/00012 ,  H01L2924/00013 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2224/05099 ,  H01L2924/00013 ,  H01L2224/05599 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A semiconductor device includes a first substrate and a second substrate. The semiconductor device includes a plurality of conductive pillars between the first and second substrates. The plurality of conductive pillars includes a first conductive pillar having a first width, wherein the first width is substantially uniform along an entire first height of the first conductive pillar, a second conductive pillar having a second width, wherein the second width is substantially uniform along an entire second height of the second conductive pillar, the first width is different from the second width, and the entire first height is equal to the entire second height, and a third conductive pillar having a third width, wherein the third width is substantially uniform along an entire third height of the third conductive pillar, and the third conductive pillar is between the first conductive pillar and the second conductive pillar in the first direction.

公开(公告)号：US11894306B2

公开(公告)日：2024-02-06

申请号：US17985827

申请日：2022-11-12

Applicant: Ping-Jung Yang

Inventor： Ping-Jung Yang

IPC: H01L23/538 ,  H01L23/15 ,  H01L23/498 ,  H10K77/10 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/5384 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H10K77/10 ,  C09K2323/00 ,  C09K2323/03 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/13005 ,  H01L2224/1308 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  Y02E10/549 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/1308 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48091 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2224/13109 ,  H01L2924/014 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2224/13005 ,  H01L2924/206 ,  H01L2224/13005 ,  H01L2924/207 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/1146 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/01029 ,  H01L2224/45139 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2224/48465 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/48465 ,  H01L2224/48091 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45124 ,  H01L2924/00014

Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.

公开(公告)号：US20230253358A1

公开(公告)日：2023-08-10

申请号：US18302935

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H01L25/10 ,  H01L29/66 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L24/17 ,  H01L23/528 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/09 ,  H01L24/14 ,  H01L24/16 ,  H01L24/33 ,  H01L24/81 ,  H01L25/105 ,  H01L25/0657 ,  H01L29/66 ,  H05K1/111 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0235 ,  H01L2224/0401 ,  H01L2224/1308 ,  H01L2224/02375 ,  H01L2224/3003 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14133 ,  H01L2224/16013 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2225/1047 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/35121 ,  H05K2201/09727 ,  H05K2201/10674

Abstract: A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

公开(公告)号：US20230223367A1

公开(公告)日：2023-07-13

申请号：US17826222

申请日：2022-05-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Luguang WANG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/81 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13124 ,  H01L2224/13181 ,  H01L2224/13166 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01073 ,  H01L2924/01022 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A semiconductor structure and a method for same are provided. The semiconductor structure includes: a first base having a first face, a second base having a second face, and a welding structure. The first base has an electrical connection column protruding from the first face. A first groove is provided at top of the electrical connection column. A conductive column is provided in the second base, and the second base also has a second groove. A top face and at least portion of a side face of the conductive column are exposed by the second groove. The electrical connection column is partially located in the second groove, and the conductive column is partially located in the first groove. At least portion of the welding structure is filled in the second groove, and at least further portion of the welding structure is filled between the conductive column and first groove.

公开(公告)号：US20190198376A1

公开(公告)日：2019-06-27

申请号：US16293201

申请日：2019-03-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Darrell D. TRUHITTE ,  James P. LETTERMAN, JR.

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11418 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27418 ,  H01L2224/2746 ,  H01L2224/27462 ,  H01L2224/276 ,  H01L2224/279 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75755 ,  H01L2224/75756 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81856 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83856 ,  H01L2224/85005 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92147 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207

Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

公开(公告)号：US20190123008A1

公开(公告)日：2019-04-25

申请号：US16221851

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yao-Chun Chuang ,  Chita Chuang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/488 ,  H01L25/10

CPC classification number: H01L24/13 ,  H01L23/488 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/141 ,  H01L2224/16104 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

公开(公告)号：US20190027459A1

公开(公告)日：2019-01-24

申请号：US16139040

申请日：2018-09-23

Applicant: Ping-Jung Yang

Inventor： Ping-Jung Yang

IPC: H01L23/00 ,  H05K1/09 ,  H01L23/15 ,  H01L23/498 ,  H01L51/00 ,  H05B33/08 ,  H01G4/12 ,  H01L25/16

CPC classification number: H01L24/30 ,  H01G4/129 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L51/0096 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05599 ,  H01L2224/056 ,  H01L2224/05688 ,  H01L2224/05788 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32151 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05B33/0896 ,  H05K1/09 ,  Y02E10/549 ,  Y02P70/521 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

公开(公告)号：US10056345B2

公开(公告)日：2018-08-21

申请号：US15243523

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tin-Hao Kuo ,  Chen-Shien Chen ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Sheng-Yu Wu ,  Yao-Chun Chuang

IPC: H01L29/49 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11903 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.

公开(公告)号：US09991224B2

公开(公告)日：2018-06-05

申请号：US15065632

申请日：2016-03-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Chen-Shien Chen

IPC: H01L21/44 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01322 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.