公开(公告)号：US5862086A

公开(公告)日：1999-01-19

申请号：US701348

申请日：1996-08-22

申请人： Chisa Makimura ,  Yukihide Suzuki ,  Shunichi Sukegawa ,  Hiroyuki Fujiwara ,  Masayuki Hira

发明人： Chisa Makimura ,  Yukihide Suzuki ,  Shunichi Sukegawa ,  Hiroyuki Fujiwara ,  Masayuki Hira

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/804 ,  G11C29/808

摘要： A semiconductor storage device is provided with a storage circuit for a faulty address and a plurality of redundant word lines corresponding to the storage circuit. The storage circuit is adapted to store a faulty address required for selecting a redundant word line. The faulty address is compared with an address input at the time of memory access by a comparator. Using a coincidence signal produced from the comparator and a predetermined address signal contained in the input address, a defect relief circuit selects one of the redundant word lines in place of the faulty word line.

摘要翻译： 半导体存储装置具有用于故障地址的存储电路和对应于存储电路的多个冗余字线。 存储电路适于存储选择冗余字线所需的故障地址。 故障地址与比较器存储器访问时的地址输入进行比较。 使用从比较器产生的符合信号和包含在输入地址中的预定地址信号，缺陷消除电路选择一个冗余字线来代替有缺陷的字线。

公开(公告)号：US5761149A

公开(公告)日：1998-06-02

申请号：US679724

申请日：1996-07-12

申请人： Yukihide Suzuki ,  Kanehide Kenmizaki ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Makoto Saeki ,  Chisa Makimura ,  Katsuo Komatsuzaki ,  Shunichi Sukegawa

发明人： Yukihide Suzuki ,  Kanehide Kenmizaki ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Makoto Saeki ,  Chisa Makimura ,  Katsuo Komatsuzaki ,  Shunichi Sukegawa

IPC分类号： H01L27/108 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/105 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C11/418 ,  G11C29/83 ,  G11C8/14 ,  H01L27/105

摘要： A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.

摘要翻译： 动态RAM具有主字线; 多个辅助字线，沿着与主字线交叉的位线的方向排列，多个动态存储单元被连接到该多个辅助字线; 多个副字选择线，其被延伸成与主字线垂直相交，并且通过该多个副字选择线发送用于选择多个辅助字线中的一个的选择信号; 以及用于从主字线接收选择信号的逻辑电路和来自每个辅助字选择线的选择信号，从而形成用于选择一个辅助字线的选择信号。 在动态RAM中，当线处于未选择状态时，使主字线和副字选择线中的每一个的电压电平等于地电位。

公开(公告)号：US08068379B1

公开(公告)日：2011-11-29

申请号：US09050946

申请日：1998-03-31

申请人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

发明人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

IPC分类号： G11C8/00

CPC分类号： H01L27/0207 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4097 ,  H01L27/10891

摘要： A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select line arranged in parallel to the main word line is extended to a plurality of sub arrays arranged in the extension direction of the word line. A second sub word select line is connected to the corresponding one of said first sub word select line to be extended orthogonally to a word line driving circuit area of an adjacent sub array. In the sub word line driving circuit provided for each sub array, a sub word line is selected and deselected by signals supplied from said main word line and said second sub word select line.

摘要翻译： 多个子字线各自具有与沿着其延伸方向的主字线的划分相等的长度，沿着与所述主字线交叉的位线布置，并且与多个存储单元连接。 与主字线平行布置的第一子字选择线被扩展到沿字线的延伸方向布置的多个子阵列。 第二子字选择线连接到所述第一子字选择线中的相应一个，以与正交相邻子阵列的字线驱动电路区域正交延伸。 在为每个子阵列提供的子字线驱动电路中，通过从所述主字线和所述第二子字选择线提供的信号来选择和取消副字线。

公开(公告)号：US6049499A

公开(公告)日：2000-04-11

申请号：US118169

申请日：1998-07-17

申请人： Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai

发明人： Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai

IPC分类号： G11C11/41 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C5/025

摘要： To reduce both the noise level according to separation or short-circuitng of the electrical supply line of the sense amplifiers and the electrical supply line of the word line driving circuit and to effectively prevent destruction of the stored data in the nonselecteded memory cell. Electrical supply line (Vssw) of the power supply voltage with respect to word line driving circuit (SWD) and electrical supply line (Vssa) of power supply voltage with respect to sense amplifier driving circuit (SAD) are arranged separately in memory array area 2 (e.g., in the space in the row direction of memory array (SMAx,y)) and connected to shared electrical supply wiring (Vsso) within peripheral circuit area 3.

摘要翻译： 为了根据读出放大器的电源线和字线驱动电路的电源线的分离或短路来降低噪声电平，并且有效地防止存储在非选择存储单元中的数据的破坏。 电源电压相对于字线驱动电路（SWD）的电源线（Vssw）和电源电压相对于读出放大器驱动电路（SAD）的供电线（Vssa）分别布置在存储器阵列区域2 （例如，在存储器阵列的行方向上的空间（SMAx，y））并且连接到外围电路区域3内的共享电源布线（Vsso）。

公开(公告)号：US6038158A

公开(公告)日：2000-03-14

申请号：US189071

申请日：1998-11-09

申请人： Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Kohji Arai

发明人： Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Kohji Arai

IPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/18 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/02 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C7/18

摘要： The objective is to realize a semiconductor memory capable of avoiding an increase in the load of the sense amplifiers, easily realizing a large capacity and high integration of the memory, reducing the current consumption by the bit lines, and improving the access speed. Because the levels of the selection signal lines SHUS1, SHUE1, SHDS1, and SHDE1 are set by the control circuit, only one of the aforementioned four selection signal lines is selected at the time of memory access, other selection signal lines are held in unselect status, and the sense amplifiers in the sense amplifier bank SB1a and prescribed bit line pairs or extended bit line pairs are connected to each other by response in order to carry out read or write; thus, the load of the sense amplifiers can be reduced, and high speed, large capacity, and high integration can be achieved.

摘要翻译： 目的是实现能够避免读出放大器的负载增加的半导体存储器，容易实现存储器的大容量和高集成度，减少位线的电流消耗，并提高存取速度。 由于选择信号线SHUS1，SHUE1，SHDS1和SHDE1的电平由控制电路设置，所以在存储器访问时仅选择上述四个选择信号线中的一个，其他选择信号线保持在取消选择状态 并且读出放大器组SB1a中的读出放大器和规定的位线对或扩展位线对通过响应彼此连接以便执行读或写; 因此能够降低读出放大器的负担，能够实现高速，大容量，高集成度。

公开(公告)号：US6002162A

公开(公告)日：1999-12-14

申请号：US90721

申请日：1998-06-04

申请人： Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai ,  Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira

发明人： Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai ,  Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira

IPC分类号： H01L21/8242 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  H01L27/108 ,  H01L29/72

CPC分类号： H01L27/10897 ,  G11C11/4074

摘要： Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect. Also, in the P well 16, in regard to the N-type MOS transistors of the sense amplifiers that undergo the substrate bias effect due to the back bias VBB, the threshold voltage is designed to a low value so as to cancel that bias effect.

摘要翻译： 通过使用于隔离的区域不必要地实现布局表面积的减小。 在该DRAM中，使用三阱结构，并且用于单位存储单元阵列MA，字线驱动器组WDB，读出放大器组SAB和交叉区域CR的所有区域被下层N- 类型深（深层）阱12.对应于字线驱动器的电源电压的背偏压VPP被施加到N阱14，并且对应于存储器单元的特性的反偏压VBB被施加到P 在N阱14中，关于由于反偏压VPP而经历衬底偏置效应的读出放大器的P型MOS晶体管，阈值电压被设置为低值，以抵消该偏置 影响。 此外，在P阱16中，关于由于背偏压VBB而经历衬底偏置效应的读出放大器的N型MOS晶体管，阈值电压被设计为低值，以抵消该偏置效应 。

公开(公告)号：US5970010A

公开(公告)日：1999-10-19

申请号：US116915

申请日：1998-07-17

申请人： Masayuki Hira ,  Shunichi Sukegawa ,  Shinji Bessho ,  Yasushi Takahashi ,  Koji Arai ,  Tsutomu Takahashi ,  Tsugio Takahashi

发明人： Masayuki Hira ,  Shunichi Sukegawa ,  Shinji Bessho ,  Yasushi Takahashi ,  Koji Arai ,  Tsutomu Takahashi ,  Tsugio Takahashi

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： Controlling the timing for the overdrive of the sense amplifiers in response to the wiring length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines.The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the wiring length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the wiring between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.

摘要翻译： 响应于读出放大器和电源电压节点之间的布线长度来控制感测放大器的过驱动的定时，以及通过防止位线的过度过载来设计功耗的降低。 根据用于驱动读出放大器和每个读出放大器组SB0至SB16的电源的供电节点CT0，CT1，CT2之间的布线长度，控制每个感测放大器组的电源电压的供应定时， 并且由于将近端的读出放大器组SB0的过驱动电压的供给时间设定得较短，并且对于过驱动电压的供给时间随着朝向远端而连续设定，所以产生于电压的感测延迟 在供电节点和感测放大器组之间的布线中产生的下降被补偿，可以实现在远端和近端的位线的过驱动的均匀性，在感测放大器组（存储单元）处的过度过驱动 垫）可以避免，并且通过扩展，可以实现功率消耗的降低。

公开(公告)号：US6097648A

公开(公告)日：2000-08-01

申请号：US66579

申请日：1998-04-24

申请人： Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai

发明人： Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4094 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4097 ,  G11C11/4094

摘要： An equalizer control line BLEQ shared by all sense amplifiers SA in each row in each submat SM is connected to a first equalizer control line driver consisting of P-type MOS transistors installed at the left end of the submat SM and is connected to several second equalizer control line drivers 32 consisting of N-type MOS transistors installed by dividing in a cross area 16 of each row through which the equalizer control line BLEQ passes. In order to turn on the equalizers of the bit line pair connected to each sense amplifier S, the first equalizer control line driver is operated to drive the equalizer control line BLEQ to the H level potential. In order to turn off the equalizers of each bit line pair, the second equalizer control line drivers 32 are operated to drive the equalizer control line BLEQ to the L level potential. The first and second equalizer control line drivers are complementarily operated. One of them is driven, and the other is turned off (blocked).

摘要翻译： 每个子矩阵SM中的每行中由所有读出放大器SA共享的均衡器控制线BLEQ连接到由安装在子矩阵SM的左端的P型MOS晶体管组成的第一均衡器控制线驱动器，并连接到多个第二均衡器 控制线驱动器32由通过在均衡器控制线BLEQ经过的每行的交叉区域16中分开安装的N型MOS晶体管组成。 为了接通连接到每个读出放大器S的位线对的均衡器，操作第一均衡器控制线驱动器以将均衡器控制线BLEQ驱动到H电平电位。 为了关闭每个位线对的均衡器，操作第二均衡器控制线驱动器32以将均衡器控制线BLEQ驱动为L电平电位。 第一和第二均衡器控制线驱动器互补操作。 其中一个被驱动，另一个被关闭（被阻止）。

公开(公告)号：US06169698A

公开(公告)日：2001-01-02

申请号：US09189076

申请日：1998-11-09

申请人： Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai

发明人： Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai

IPC分类号： G11C700

CPC分类号： G11C5/063 ,  G11C5/143 ,  G11C5/147 ,  G11C7/06

摘要： Drop in the power supply level right after change can be suppressed greatly when changing the power to the internal power supply voltage from the external power supply voltage of an overdrive system. Voltage generating circuit VG0 is connected to the VDL line which raises the VDL line to a voltage higher than VDL beforehand prior to changing to internal power supply voltage VDL from external power supply voltage VDD, and restores the VDL line voltage which drops after the change to VDL. More specifically, there are detecting circuit part 40 which detects the VDL line potential, first switching element M1 connected between the VDL line and the VDD line and which operates according to the detected result of detecting circuit part 40, and second switching element M2 connected between common voltage VSS and connection node ND1 between first switching element M1 and detecting circuit part 40, which changes the potential of connection node ND1 by conducting according to input preliminary voltage step up signal MVDL, and by it conducts first switching element M1 for a fixed time.

摘要翻译： 在从过驱动系统的外部电源电压改变内部电源电压的电源时，可以大幅度地抑制变更后的电源电平下降。 在从外部电源电压VDD变为内部电源电压VDL之前，将电压生成电路VG0与VDL线连接，将VDL线预先升压至高于VDL的电压，并且将变更后降低的VDL线电压恢复为 VDL。 更具体地，存在检测VDL线电位的检测电路部40，连接在VDL线与VDD线之间的第一开关元件M1，其根据检测电路部40的检测结果进行动作，第二开关元件M2连接在 第一开关元件M1和检测电路部分40之间的公共电压VSS和连接节点ND1，其通过根据输入的初步升压信号MVDL进行导通来改变连接节点ND1的电位，并且通过其将第一开关元件M1导通固定时间 。

公开(公告)号：US6031779A

公开(公告)日：2000-02-29

申请号：US058147

申请日：1998-04-10

申请人： Yasushi Takahashi ,  Tsutomu Takahashi ,  Kouji Arai ,  Tsugio Takahashi ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

发明人： Yasushi Takahashi ,  Tsutomu Takahashi ,  Kouji Arai ,  Tsugio Takahashi ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C8/14 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/408 ,  G11C7/06 ,  G11C8/14 ,  G11C2207/065

摘要： Described herein is a dynamic memory. An N channel type voltage clamp MOSFET is provided which has a drain supplied with a supply voltage supplied from an external terminal, a gate to which a boosted constant voltage is applied, and a source which outputs a constant voltage. The clamp voltage outputted from the source of the voltage clamp MOSFET is supplied to a common source line for each of P channel type amplification MOSFETs constituting a sense amplifier via a P channel type first power MOSFET switch-controlled by a sense amplifier activation signal, as a voltage for operating the sense amplifier. Further, the constant voltage outputted from the source of the voltage clamp MOSFET is supplied to an N-well region in which the P channel type first power MOSFET and the P channel type MOSFETs constituting the sense amplifier are formed, as a bias voltage.

摘要翻译： 这里描述的是动态存储器。 提供了一种N沟道型电压钳位MOSFET，其具有供给从外部端子提供的电源电压的漏极，施加升压恒定电压的栅极和输出恒定电压的源极。 从电压钳位MOSFET的源极输出的钳位电压通过由读出放大器激活信号开关控制的P沟道型第一功率MOSFET构成读出放大器的每个P沟道型放大器MOSFET，被提供给公共源极线，如 用于操作读出放大器的电压。 此外，从电压钳位MOSFET的源极输出的恒定电压被提供给形成P沟道型第一功率MOSFET和构成读出放大器的P沟道型MOSFET的N阱区域作为偏置电压。