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    Trench IGBT for highly capacitive loads
    1.
    发明申请
    Trench IGBT for highly capacitive loads 有权
    用于高容性负载的沟槽IGBT

    公开(公告)号：US20070085148A1

    公开(公告)日：2007-04-19

    申请号：US11252642

    申请日：2005-10-18

    Applicant: Chiu Ng ,  Davide Chiola

    Inventor： Chiu Ng ,  Davide Chiola

    IPC: H01L31/00

    CPC classification number: H01L29/7397 ,  H01L29/402 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An IGBT for controlling the application of power to a plasma display panel has an increased current conduction capability and a reduced conduction loss at the expense of a reduced safe operating area. For a device with a 300 volt breakdown voltage rating, the die has a substrate resistivity less than 10 m ohm cm; a buffer layer thickness of about 8 μm resistivity in the range of 0.05 to 0.10 ohm cm, and an epi layer for receiving junction patterns and trenches, which has a thickness of from 31 to 37 μm and resistivity in te range of 14 to 18 ohm cm.

    Abstract translation: 用于控制对等离子体显示面板的电力施加的IGBT具有增加的导电能力和降低的传导损耗，而降低安全操作区域。 对于具有300伏击穿电压额定值的器件，裸片具有小于10mΩcm的衬底电阻; 具有约0.05μm至0.10欧姆cm范围内的约8μm电阻率的缓冲层厚度，以及用于接收结形图案和沟槽的外延层，其厚度为31至37μm，电阻率范围为14至18欧姆 厘米。

    Trench IGBT for highly capacitive loads
    2.
    发明授权
    Trench IGBT for highly capacitive loads 有权
    用于高容性负载的沟槽IGBT

    公开(公告)号：US07655977B2

    公开(公告)日：2010-02-02

    申请号：US11252642

    申请日：2005-10-18

    Applicant: Chiu Ng ,  Davide Chiola

    Inventor： Chiu Ng ,  Davide Chiola

    IPC: H01L23/62

    CPC classification number: H01L29/7397 ,  H01L29/402 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An IGBT for controlling the application of power to a plasma display panel has an increased current conduction capability and a reduced conduction loss at the expense of a reduced safe operating area. For a device with a 300 volt breakdown voltage rating, the die has a substrate resistivity less than 10 m ohm cm; a buffer layer thickness of about 8 μm resistivity in the range of 0.05 to 0.10 ohm cm, and an epi layer for receiving junction patterns and trenches, which has a thickness of from 31 to 37 μm and resistivity in te range of 14 to 18 ohm cm.

    Abstract translation: 用于控制对等离子体显示面板的电力施加的IGBT具有增加的导电能力和降低的传导损耗，而降低安全操作区域。 对于具有300伏击穿电压额定值的器件，裸片具有小于10mΩcm的衬底电阻; 具有约0.05μm至0.10欧姆cm范围内的约8μm电阻率的缓冲层厚度，以及用于接收结形图案和沟槽的外延层，其厚度为31至37μm，电阻率范围为14至18欧姆 厘米。

    Merged P-i-N Schottky structure
    4.
    发明授权
    Merged P-i-N Schottky structure 有权
    合并的P-i-N肖特基结构

    公开(公告)号：US07858456B2

    公开(公告)日：2010-12-28

    申请号：US11402039

    申请日：2006-04-11

    Applicant: Davide Chiola ,  Kohji Andoh ,  Silvestro Fimiani

    Inventor： Davide Chiola ,  Kohji Andoh ,  Silvestro Fimiani

    IPC: H01L21/338

    CPC classification number: H01L29/872 ,  H01L27/0814 ,  H01L29/0684 ,  H01L29/868

    Abstract: Merged P-i-N Schottky device in which the oppositely doped diffusions extend to a depth and have been spaced apart such that the device is capable of absorbing a reverse avalanche energy comparable to a Fast Recovery Epitaxial Diode having a comparatively deeper oppositely doped diffusion region.

    Abstract translation: 合并的P-i-N肖特基器件，其中相反掺杂的扩散延伸到深度并且已经间隔开，使得该器件能够吸收与具有相对更深的相反掺杂扩散区域的快速恢复外延二极管相当的反向雪崩能量。

    Trench Schottky barrier diode with differential oxide thickness
    5.
    发明授权
    Trench Schottky barrier diode with differential oxide thickness 有权

    公开(公告)号：US07323402B2

    公开(公告)日：2008-01-29

    申请号：US11035582

    申请日：2005-01-14

    Applicant: Davide Chiola

    Inventor： Davide Chiola

    IPC: H01L21/28 ,  H01L21/44

    CPC classification number: H01L29/8725 ,  H01L27/0814 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/872 ,  Y10S438/963

    Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.

    Method for producing a semiconductor component
    7.
    发明授权
    Method for producing a semiconductor component 有权
    半导体部件的制造方法

    公开(公告)号：US08003456B2

    公开(公告)日：2011-08-23

    申请号：US12145808

    申请日：2008-06-25

    Applicant: Davide Chiola ,  Carsten Schaeffer

    Inventor： Davide Chiola ,  Carsten Schaeffer

    IPC: H01L21/8238

    CPC classification number: H01L29/7397 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/66348

    Abstract: A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step.

    Abstract translation: 提出了半导体元件的制造方法。 该方法包括提供具有第一表面的半导体本体; 在所述第一表面上形成掩模，其中所述掩模具有用于限定沟槽的相应位置的开口; 使用掩模在半导体本体中产生沟槽，其中台面结构保留在相邻的沟槽之间; 使用掩模将第一导电类型的第一掺杂剂引入沟槽的底部; 进行第一热步骤; 将与第一导电类型互补的第二导电类型的第二掺杂剂至少引入到沟槽的底部; 并进行第二热步骤。

    Trench Schottky barrier diode with differential oxide thickness
    9.
    发明申请
    Trench Schottky barrier diode with differential oxide thickness 有权
    具有差异氧化物厚度的沟槽肖特基势垒二极管

    公开(公告)号：US20080087896A1

    公开(公告)日：2008-04-17

    申请号：US11974103

    申请日：2007-10-11

    Applicant: Davide Chiola

    Inventor： Davide Chiola

    IPC: H01L31/00 ,  H01L29/00 ,  H01L31/07 ,  H01L31/108

    CPC classification number: H01L29/8725 ,  H01L27/0814 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/872 ,  Y10S438/963

    Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.

    Abstract translation: 在沟槽内具有差的氧化物厚度的沟槽肖特基二极管的制造方法包括在衬底表面上形成第一氮化物层，并且随后在衬底中形成多个沟槽，包括可能的端接沟槽。 在牺牲氧化层形成和去除之后，沟槽的侧壁和底表面被氧化。 然后将第二氮化物层施加到衬底并被蚀刻，使得第二氮化物层覆盖沟槽侧壁上的氧化物层，但是暴露出沟槽底表面上的氧化物层。 然后，沟槽底表面被再次氧化，然后从侧壁去除剩余的第二氮化物层，导致在每个沟槽的侧壁和底表面上形成不同厚度的氧化物层。 然后用P型多晶硅，去除第一氮化物层和施加到衬底表面上的肖特基势垒金属填充沟槽。

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