公开(公告)号：US20170345475A1

公开(公告)日：2017-11-30

申请号：US15402231

申请日：2017-01-09

申请人： Choong-Jae LEE ,  Gwan-Hyeob KOH ,  Bo-Young SEO ,  Yong-Kyu LEE

发明人： Choong-Jae LEE ,  Gwan-Hyeob KOH ,  Bo-Young SEO ,  Yong-Kyu LEE

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/22 ,  G11C13/0002

摘要： A resistive-type memory device is disclosed. The resistive-type memory device includes a memory cell array and a control logic circuit. The control logic circuit accesses the memory cell array in response to a command and an address provided from an outside. The memory cell array includes at least a first group of resistive-type memory cells and a second group of resistive-type memory cells. Each of the first group of resistive-type memory cells has a first feature size and each of the second group of resistive-type memory cells has a second feature size that is different from the first feature size.

公开(公告)号：US20160086565A1

公开(公告)日：2016-03-24

申请号：US14857926

申请日：2015-09-18

申请人： Seong-Young RYU ,  Yong-Kyu LEE ,  Choong-Jae LEE

发明人： Seong-Young RYU ,  Yong-Kyu LEE ,  Choong-Jae LEE

IPC分类号： G09G5/00 ,  G06F3/041 ,  G06F1/32

CPC分类号： G09G5/003 ,  G06F1/3265 ,  G06F3/0412 ,  G06F3/0416 ,  G09G5/006 ,  G09G2330/021 ,  G09G2340/16 ,  G09G2360/18 ,  G09G2370/10 ,  Y02D10/153

摘要： A display driving circuit includes a frame buffer that stores a plurality of pieces of line data, and a buffer controller. The buffer controller receives a data packet, and outputs first line data included in the data packet or second line data stored in the frame buffer as grayscale data based on flag information included in the data packet.

摘要翻译： 显示驱动电路包括存储多条线数据的帧缓冲器和缓冲器控制器。 缓冲器控制器接收数据包，并且基于包括在数据包中的标志信息，输出包含在数据包中的第一行数据或存储在帧缓冲器中的第二行数据作为灰度数据。

公开(公告)号：US20140198560A1

公开(公告)日：2014-07-17

申请号：US14083569

申请日：2013-11-19

申请人： Choong-Jae LEE ,  Kyoung-Mok SON ,  Sang-Gi KO ,  Si-Woo KIM

发明人： Choong-Jae LEE ,  Kyoung-Mok SON ,  Sang-Gi KO ,  Si-Woo KIM

IPC分类号： G11C11/4096

CPC分类号： G11C8/16 ,  G11C11/403 ,  H01L27/10805 ,  H01L27/1156

摘要： A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.

摘要翻译： 存储单元包括金属氧化物半导体（MOS）电容器，其包括耦合到存储节点的栅极和耦合到同步控制线的电极。 MOS电容器基于同步控制线上的电压变化，向栅极增加耦合电压。 耦合电压可以将存储节点维持在预定范围内。