公开(公告)号：US06903412B2

公开(公告)日：2005-06-07

申请号：US10106812

申请日：2002-03-26

申请人： Mohamed N. Darwish ,  Christiana Yue ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill ,  Deva N. Pattanayak

发明人： Mohamed N. Darwish ,  Christiana Yue ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill ,  Deva N. Pattanayak

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28238 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66621 ,  H01L29/7834

摘要： The gate oxide layer of a trench MIS device includes a graduated transition region, where the thickness of the gate oxide layer decreases gradually from a thick section adjacent the bottom of the trench to a thin section adjacent the sidewall of the trench. The PN junction between the body and drain regions intersects the trench in the transition region. This structure allows for a greater margin of error in the placement of the PN junction during the manufacture of the device, since the intersection between the PN junction can be located anywhere in the transition region. The MIS device also has improved breakdown characteristics.

摘要翻译： 沟槽MIS器件的栅极氧化层包括刻蚀过渡区域，其中栅极氧化物层的厚度从邻近沟槽底部的厚部分逐渐减小到邻近沟槽侧壁的薄部分。 体区和漏区之间的PN结与过渡区中的沟槽相交。 这种结构允许在器件制造期间在PN结的放置方面具有更大的误差余量，因为PN结的交点可位于过渡区域的任何地方。 MIS器件还具有改善的击穿特性。

公开(公告)号：US06875657B2

公开(公告)日：2005-04-05

申请号：US10106896

申请日：2002-03-26

申请人： Christiana Yue ,  Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill ,  Deva N. Pattanayak

发明人： Christiana Yue ,  Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill ,  Deva N. Pattanayak

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28238 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66621 ,  H01L29/7834

摘要： A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to “lift off”, creating a “bird's beak” structure. This becomes a “transition region”, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error. This improves the manufacturability of the device and enhances its breakdown characteristics.

摘要翻译： 用于制造沟槽MIS器件的工艺包括在沟槽中沉积共形氮化物层; 蚀刻氮化物层以在沟槽的底部产生暴露区域; 并加热衬底，从而在暴露区域中生长氧化物层。 该过程使掩模层“脱落”，形成“鸟的喙”结构。 这成为“过渡区域”，其中氧化物层的厚度在远离曝光区域的方向上逐渐减小。 该方法还包括将掺杂剂扩散到衬底中，掺杂剂与所述衬底的剩余部分形成PN结，并且控制扩散，使得PN结与过渡区域中的沟槽相交。 因为氧化物层的厚度逐渐减小，所以PN结不需要位于特定的位置，即存在误差范围。 这提高了器件的可制造性并增强了其击穿特性。

公开(公告)号：US06709930B2

公开(公告)日：2004-03-23

申请号：US10176570

申请日：2002-06-21

申请人： Ben Chan ,  Kam Hong Lui ,  Christiana Yue ,  Ronald Wong ,  David Chang ,  Frederick P. Giles ,  Kyle Terrill ,  Mohamed N. Darwish ,  Deva Pattanayak ,  Robert Q. Xu ,  Kuo-in Chen

发明人： Ben Chan ,  Kam Hong Lui ,  Christiana Yue ,  Ronald Wong ,  David Chang ,  Frederick P. Giles ,  Kyle Terrill ,  Mohamed N. Darwish ,  Deva Pattanayak ,  Robert Q. Xu ,  Kuo-in Chen

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368

摘要： A trench MOSFET is formed by creating a trench in a semiconductor substrate, then forming a barrier layer over a portion of the side wall of the trench. A thick insulating layer is deposited in the bottom of the trench. The barrier layer is selected such that the thick insulating layer deposits in the bottom of the trench at a faster rate than the thick insulating layer deposits on the barrier layer. Embodiments of the present invention avoid stress and reliability problems associated with thermal growth of insulating layers, and avoid problems with control of the shape and thickness of the thick insulating layer encountered when a thick insulating layer is deposited, then etched to the proper shape and thickness.

摘要翻译： 通过在半导体衬底中形成沟槽，然后在沟槽的侧壁的一部分上形成阻挡层来形成沟槽MOSFET。 在沟槽的底部沉积厚的绝缘层。 选择阻挡层使得厚的绝缘层以比绝缘层沉积在阻挡层上更快的速率沉积在沟槽的底部。 本发明的实施例避免了与绝缘层的热生长相关的应力和可靠性问题，并且避免了当沉积厚绝缘层时遇到的厚绝缘层的形状和厚度的控制问题，然后蚀刻到适当的形状和厚度 。

公开(公告)号：US07012005B2

公开(公告)日：2006-03-14

申请号：US10180154

申请日：2002-06-25

申请人： Karl Lichtenberger ,  Frederick P. Giles ,  Christiana Yue ,  Kyle Terrill ,  Mohamed N. Darwish ,  Deva Pattanayak ,  Kam Hong Lui ,  Robert Q. Xu ,  Kuo-in Chen

发明人： Karl Lichtenberger ,  Frederick P. Giles ,  Christiana Yue ,  Kyle Terrill ,  Mohamed N. Darwish ,  Deva Pattanayak ,  Kam Hong Lui ,  Robert Q. Xu ,  Kuo-in Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28211 ,  H01L21/2822 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368

摘要： In accordance with the present invention, a trench MOSFET is formed by creating a trench in a semiconductor substrate. A portion of either a side wall of the trench or the bottom of the trench is implanted with an implant species. An insulating layer is then grown overlying the bottom and side wall of the trench. The implant species is selected such that the insulating layer grows more quickly on the bottom of the trench than on the side wall of the trench, resulting in a thicker insulating layer in the bottom of the trench than on the trench side walls.

公开(公告)号：US06921697B2

公开(公告)日：2005-07-26

申请号：US10264816

申请日：2002-10-03

申请人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

发明人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

摘要： Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

摘要翻译： 公开了包括沟槽底部的厚绝缘层的沟槽MIS装置以及制造这种装置的方法。 示例性沟槽MOSFET实施例包括在沟槽底部的厚氧化物层，沿着沟槽底部在衬底中的应力没有明显变化。 厚的绝缘层将沟槽栅极与沟槽底部的漏极区分离，从而产生减小的栅 - 漏电容，从而使得适合于高频应用的MOSFET。 在示例性制造工艺实施例中，厚绝缘层沉积在沟槽的底部。 在暴露的侧壁上形成薄的绝缘栅极电介质，并且耦合到厚的绝缘层。 在剩余的沟槽体积中形成栅极。 该过程完成与身体和源植入物，钝化和金属化。

公开(公告)号：US06882000B2

公开(公告)日：2005-04-19

申请号：US09927320

申请日：2001-08-10

申请人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

发明人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

摘要： Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

摘要翻译： 公开了包括沟槽底部的厚绝缘层的沟槽MIS装置以及制造这种装置的方法。 示例性沟槽MOSFET实施例包括在沟槽底部的厚氧化物层，沿着沟槽底部在衬底中的应力没有明显变化。 厚的绝缘层将沟槽栅极与沟槽底部的漏极区分离，从而产生减小的栅 - 漏电容，从而使得适合于高频应用的MOSFET。 在示例性制造工艺实施例中，厚绝缘层沉积在沟槽的底部。 在暴露的侧壁上形成薄的绝缘栅极电介质，并且耦合到厚的绝缘层。 在剩余的沟槽体积中形成栅极。 该过程完成与身体和源植入物，钝化和金属化。

公开(公告)号：US06849898B2

公开(公告)日：2005-02-01

申请号：US09927143

申请日：2001-08-10

申请人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

发明人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28238 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66621 ,  H01L29/7834

摘要： Trench MOSFETs including active corner regions and a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such MOSFETs. In an exemplary embodiment, the trench MOSFET includes a thick insulative layer centrally located at the bottom of the trench. A thin gate insulative layer lines the sidewall and a peripheral portion of the bottom surface of the trench. A gate fills the trench, adjacent to the gate insulative layer. The gate is adjacent to the sides and top of the thick insulative layer. The thick insulative layer separates the gate from the drain conductive region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications.

摘要翻译： 公开了在沟槽底部包括有源角区和厚绝缘层的沟槽MOSFET以及制造这种MOSFET的方法。 在示例性实施例中，沟槽MOSFET包括位于沟槽底部中心的厚绝缘层。 薄栅极绝缘层将沟槽的侧壁和底部表面的周边部分排列。 栅极填充与栅极绝缘层相邻的沟槽。 栅极与厚绝缘层的侧面和顶部相邻。 厚绝缘层将栅极与沟槽底部的漏极导电区域分离，从而产生降低的栅极 - 漏极电容，从而形成适合高频应用的MOSFET。