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15 条记录 (耗时 0.043 秒)

    Method for making trench MIS device with reduced gate-to-drain capacitance
    5.
    发明授权
    Method for making trench MIS device with reduced gate-to-drain capacitance 有权
    制造具有降低的栅极 - 漏极电容的沟道MIS器件的方法

    公开(公告)号：US06921697B2

    公开(公告)日：2005-07-26

    申请号：US10264816

    申请日：2002-10-03

    申请人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

    发明人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

    IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

    摘要： Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

    摘要翻译： 公开了包括沟槽底部的厚绝缘层的沟槽MIS装置以及制造这种装置的方法。 示例性沟槽MOSFET实施例包括在沟槽底部的厚氧化物层，沿着沟槽底部在衬底中的应力没有明显变化。 厚的绝缘层将沟槽栅极与沟槽底部的漏极区分离，从而产生减小的栅 - 漏电容，从而使得适合于高频应用的MOSFET。 在示例性制造工艺实施例中，厚绝缘层沉积在沟槽的底部。 在暴露的侧壁上形成薄的绝缘栅极电介质，并且耦合到厚的绝缘层。 在剩余的沟槽体积中形成栅极。 该过程完成与身体和源植入物，钝化和金属化。

    Trench MIS device with reduced gate-to-drain capacitance
    6.
    发明授权
    Trench MIS device with reduced gate-to-drain capacitance 有权
    沟槽MIS器件具有降低的栅极 - 漏极电容

    公开(公告)号：US06882000B2

    公开(公告)日：2005-04-19

    申请号：US09927320

    申请日：2001-08-10

    申请人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

    发明人： Mohamed N. Darwish ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill

    IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

    摘要： Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

    摘要翻译： 公开了包括沟槽底部的厚绝缘层的沟槽MIS装置以及制造这种装置的方法。 示例性沟槽MOSFET实施例包括在沟槽底部的厚氧化物层，沿着沟槽底部在衬底中的应力没有明显变化。 厚的绝缘层将沟槽栅极与沟槽底部的漏极区分离，从而产生减小的栅 - 漏电容，从而使得适合于高频应用的MOSFET。 在示例性制造工艺实施例中，厚绝缘层沉积在沟槽的底部。 在暴露的侧壁上形成薄的绝缘栅极电介质，并且耦合到厚的绝缘层。 在剩余的沟槽体积中形成栅极。 该过程完成与身体和源植入物，钝化和金属化。

    Super trench MOSFET including buried source electrode and method of fabricating the same
    10.
    发明授权
    Super trench MOSFET including buried source electrode and method of fabricating the same 有权
    包括埋地源极的超级沟槽MOSFET及其制造方法

    公开(公告)号：US07183610B2

    公开(公告)日：2007-02-27

    申请号：US10836833

    申请日：2004-04-30

    申请人： Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

    发明人： Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

    摘要： In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

    摘要翻译： 在沟槽MOSFET中，沟槽的下部包含与外延层和半导体衬底绝缘但与源极区域电接触的掩埋源电极。 当MOSFET处于“关闭”状态时，掩埋源电极的偏置导致台面的“漂移”区域耗尽，增强了MOSFET阻止电流的能力。 因此，可以增加漂移区的掺杂浓度，从而降低MOSFET的导通电阻。 埋入式源极还降低了MOSFET的栅 - 漏电容，提高了MOSFET在高频下的工作能力。 衬底可以有利地包括由环形台面分隔开的多个环形沟槽和从源极金属区域分开的多个栅极金属腿中的中心区域向外延伸的栅极金属层。