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1.发明授权Integrated processor and programmable data path chip for reconfigurable computing 失效集成处理器和可编程数据路径芯片，用于可重新配置的计算
公开(公告)号：US5970254A
公开(公告)日：1999-10-19
申请号：US884380
申请日：1997-06-27
CPC分类号： G06F15/7867
摘要： A reconfigurable processor chip has a mixture of reconfigurable arithmetic cells and logic cells for higher effective utilization than a standard FPGA. The reconfigurable processor includes a standard microprocessor such as an embedded RISC processor. Many different types of interfaces are used to interface between the embedded processor and the reconfigurable portions of the chip, thus allowing for the fastest interface between standard processor code and configurable "hard-wired" functions. A configuration memory stack is provided, allowing for nearly instantaneous reconfiguration. if desired, configuration planes can be shared between ALU function configuration and bus interconnect configuration, allowing more efficient use of stack memory.
摘要翻译： 可重配置处理器芯片具有可重构算术单元和逻辑单元的混合，用于比标准FPGA更高的有效利用率。 可重构处理器包括诸如嵌入式RISC处理器的标准微处理器。 许多不同类型的接口用于在嵌入式处理器和芯片的可重新配置部分之间进行接口，从而允许标准处理器代码和可配置的“硬连线”功能之间的最快接口。 提供配置存储器堆栈，允许几乎瞬时重新配置。 如果需要，可以在ALU功能配置和总线互连配置之间共享配置平面，从而更有效地使用堆栈内存。
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2.发明授权Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic 失效将高级编程语言编译成具有多重可重构逻辑的嵌入式微处理器的方法公开(公告)号：US06708325B2
公开(公告)日：2004-03-16
申请号：US09446758
申请日：2000-05-31
IPC分类号： G06F944
CPC分类号： G06F17/5045 , G06F8/4441 , G06F8/447 , G06F8/451 , G06F9/30181
摘要： A computer implemented method for automatically compiling a computer program written in a high level programming language into an intermediate data structure. The data structure is analyzed to identify critical blocks of logic, which can be implemented as an application specific integrated circuit (ASIC), to improve overall performance. The critical blocks of logic are transformed into new equivalent logic with maximal data parallelism. The parallelized logic is then translated into a Boolean gate representation, which is suitable for implementation on an ASIC. The ASIC may be coupled with a generic microprocessor via custom instruction for the microprocessor. The original computer program is then compiled into object code with the new expanded target instruction set.
摘要翻译： 一种用于将以高级编程语言编写的计算机程序自动编译成中间数据结构的计算机实现的方法。 分析数据结构以识别关键的逻辑块，其可以被实现为专用集成电路（ASIC），以提高整体性能。 逻辑的关键块被转换成具有最大数据并行性的新的等效逻辑。 然后将并行化逻辑转换为布尔门表示，适用于ASIC上的实现。 ASIC可以通过微处理器的定制指令与通用微处理器耦合。 然后将原始计算机程序用新的扩展目标指令集编译成目标代码。
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3.发明授权Method for compiling high level programming languages into an integrated processor with reconfigurable logic 失效将高级编程语言编译成具有可重构逻辑的集成处理器的方法
公开(公告)号：US5966534A
公开(公告)日：1999-10-12
申请号：US884377
申请日：1997-06-27
CPC分类号： G06F17/5045 , G06F8/4441 , G06F8/447 , G06F8/451
摘要： A method is presented for automatically compiling a high level computer program down into an application specific integrated circuit coupled with a generic microprocessor. The original source code is written in a standard programming language such as ANSI C. Source code analysis is performed by our compiler to automatically determine which blocks of logic are most appropriate for the application specific integrated circuit and which for the generic microprocessor. The complete layout of the application specific integrated circuit is automatically generated by our compiler. Object code for the microprocessor, with custom instructions to invoke the application specific integrated circuit, is also automatically generated by our compiler.
摘要翻译： 提出了一种用于将高级计算机程序自动编译成与通用微处理器耦合的专用集成电路的方法。 原始源代码以标准编程语言（如ANSI C）编写。源代码分析由我们的编译器执行，以自动确定哪个逻辑块最适合于专用集成电路以及通用微处理器。 专用集成电路的完整布局由我们的编译器自动生成。 微处理器的对象代码，具有调用专用集成电路的自定义指令，也由我们的编译器自动生成。
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公开(公告)号：US06389579B1
公开(公告)日：2002-05-14
申请号：US09238648
申请日：1999-01-26
IPC分类号： G06F1750
CPC分类号： G06F1/035 , G06F15/7867
摘要： An integrated circuit which contains a processor, and configurable logic with configuration memory such that the configurable logic can emulate a large memory array when the contents of the array are very sparse. This structure allows for fast access and a continuous updating capability while remaining internal to the chip. A methodology for recompressing the contents of the configurable logic while updating the configurable logic is also described.
摘要翻译： 包含处理器的集成电路和具有配置存储器的可配置逻辑，使得当阵列的内容非常稀疏时，可配置逻辑可以模拟大的存储器阵列。 该结构允许在芯片内部保持快速访问和连续更新能力。 还描述了在更新可配置逻辑时重新压缩可配置逻辑的内容的方法。
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5.发明授权Integrated processor and programmable data path chip for reconfigurable computing 失效集成处理器和可编程数据路径芯片，用于可重新配置的计算公开(公告)号：US06282627B1
公开(公告)日：2001-08-28
申请号：US09446762
申请日：2000-05-25
IPC分类号： G06F1314
CPC分类号： G06F15/7867 , G06F9/3879 , G06F9/3885 , G06F9/3897
摘要： The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (1101, 1103), and interfaces (319a, 319b, 311) between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different portions of ALU functions and bus interconnect. Many types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and configurable “hard-wired” functions.
摘要翻译： 本发明一般地提供了可重新配置的计算解决方案，其提供软件开发的灵活性和专用硬件解决方案的性能。 可重构处理器芯片包括标准处理器，这些元件之间的可重构逻辑块（1101,1103）和接口（319a，319b，311）。 该芯片允许使用相应的软件工具将应用程序代码重新编译为软件和可重新加载的硬件块的组合。 算术单元和逻辑单元的混合允许比标准互连更高效地利用硅。 更有效地使用配置堆栈存储器结果，因为转换代码的不同部分需要ALU功能和总线互连的不同部分。 提供了与嵌入式处理器的许多类型的接口，允许标准处理器代码和可配置的“硬连线”功能之间的快速接口。
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公开(公告)号：US5671234A
公开(公告)日：1997-09-23
申请号：US78692
申请日：1993-06-17
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H03K17/693 , H03K19/00 , H03K19/003 , H03K19/0185 , H03K19/173
CPC分类号： H03K17/693 , H03K19/00361 , H03K19/018585
摘要： An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.
摘要翻译： 具有可编程元件的系统逻辑的集成电路，耦合到可编程元件的解码逻辑，用于寻址可编程元件;以及多个输入/输出缓冲电路，用于通过输入/输出端子在集成电路的系统逻辑与外部之间传递信号 被披露。 每个输入/输出缓冲电路包括具有连接到输入/输出端子的输出端的输出驱动级; 多个单元，每个单元具有多路复用器，连接到第一多路复用器的输出端的触发器，用于存储来自第一多路复用器的信号;连接到触发器的输出端的锁存器，用于存储信号 以及连接到锁存器的输出端的第二多路复用器。 这些单元彼此连接，其它输入/输出缓冲电路的单元从一个单元的触发器的输出端子连接到另一个单元的第一多路复用器的第一输入端，用于通过单元串行扫描信号，以测试 系统逻辑。 控制线连接到单元的锁存器的输出端子和耦合到可编程元件的解码逻辑，使得可编程元件可以通过串行扫描通过单元的控制信号进行编程。
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公开(公告)号：US5652527A
公开(公告)日：1997-07-29
申请号：US466556
申请日：1995-06-06
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H03K17/693 , H03K19/00 , H03K19/003 , H03K19/0185 , H03K19/173 , H03K19/01 , H03K19/0175
CPC分类号： H03K17/693 , H03K19/00361 , H03K19/018585
摘要： An input/output circuit for increasing immunity to voltage spikes from voltage supplies is provided. The circuit includes a first pair of transistors each having their drains connected to an output terminal and their sources connected to voltage supplies. A mechanism is connected to electrically separated voltage supplies to alternately turn on one of the first pair of transistors responsive to an input signal. A transistor is utilized to provide feedback to limit the rise in a ground voltage supply as occurs during ground bounce.
摘要翻译： 提供了用于增加对电压源的电压尖峰的抗扰度的输入/输出电路。 电路包括第一对晶体管，每个晶体管的漏极连接到输出端，并且其源极连接到电压源。 机构连接到电分离的电压源，以响应于输入信号交替地接通第一对晶体管中的一个。 晶体管被用于提供反馈以限制地面反弹期间出现的接地电压供应的上升。
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公开(公告)号：US5534798A
公开(公告)日：1996-07-09
申请号：US467340
申请日：1995-06-06
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H03K17/693 , H03K19/00 , H03K19/003 , H03K19/0185 , H03K19/173 , H03K19/084 , H03K19/094
CPC分类号： H03K17/693 , H03K19/00361 , H03K19/018585
摘要： An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.
摘要翻译： 具有可编程元件的系统逻辑的集成电路，耦合到可编程元件的解码逻辑，用于寻址可编程元件;以及多个输入/输出缓冲电路，用于通过输入/输出端子在集成电路的系统逻辑与外部之间传递信号 被披露。 每个输入/输出缓冲电路包括具有连接到输入/输出端子的输出端的输出驱动级; 多个单元，每个单元具有多路复用器，连接到第一多路复用器的输出端的触发器，用于存储来自第一多路复用器的信号;连接到触发器的输出端的锁存器，用于存储信号 以及连接到锁存器的输出端的第二多路复用器。 这些单元彼此连接，其它输入/输出缓冲电路的单元从一个单元的触发器的输出端子连接到另一个单元的第一多路复用器的第一输入端，用于通过单元串行扫描信号，以测试 系统逻辑。 控制线连接到单元的锁存器的输出端子和耦合到可编程元件的解码逻辑，使得可编程元件可以通过串行扫描通过单元的控制信号进行编程。
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公开(公告)号：US5347519A
公开(公告)日：1994-09-13
申请号：US801237
申请日：1991-12-03
IPC分类号： G01R31/28 , G01R31/30 , G01R31/317 , G01R31/3185 , G06F11/22 , H03K19/177 , H04B17/00
CPC分类号： G01R31/318519 , G01R31/31727 , G01R31/318536 , G01R31/30 , G01R31/318516 , G06F2201/88
摘要： A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series transistors and latch logic blocks may be tested together with the continuity of their programmable connections. Programmable input/output buffer circuits and clock circuits which set the desired clock network paths may be tested with signals on a serial scan path which passes through the input/output buffer circuits and clock circuits. Process characterization tests without the requirement of high-speed test equipment are also provided.
摘要翻译： 提供了一种现场可编程门阵列集成电路，其在编程集成电路中的反熔丝之前具有许多用于测试的特征。 用于编程反熔丝的电路也用于大量的预编程测试。 连续串联晶体管和锁存逻辑块的功能可以与其可编程连接的连续性一起进行测试。 可以通过串行扫描路径上通过输入/输出缓冲电路和时钟电路的信号测试设置所需时钟网络路径的可编程输入/输出缓冲电路和时钟电路。 还提供了无需高速测试设备的过程表征测试。
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公开(公告)号：US5221865A
公开(公告)日：1993-06-22
申请号：US718677
申请日：1991-06-21
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H03K17/693 , H03K19/00 , H03K19/003 , H03K19/0185 , H03K19/173
CPC分类号： H03K17/693 , H03K19/00361 , H03K19/018585
摘要： An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the first storing means for storing a signal from the first storing means, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.
摘要翻译： 具有可编程元件的系统逻辑的集成电路，耦合到可编程元件的解码逻辑，用于寻址可编程元件;以及多个输入/输出缓冲电路，用于通过输入/输出端子在集成电路的系统逻辑与外部之间传递信号 被披露。 每个输入/输出缓冲电路包括具有连接到输入/输出端子的输出端的输出驱动级; 以及多个单元，每个单元具有多路复用器，连接到第一多路复用器的输出端的触发器，用于存储来自第一多路复用器的信号;锁存器，连接到第一存储装置的输出端，用于存储信号 以及连接到所述锁存器的输出端的第二多路复用器。 这些单元彼此连接，其它输入/输出缓冲电路的单元从一个单元的触发器的输出端子连接到另一个单元的第一多路复用器的第一输入端，用于通过单元串行扫描信号，以测试 系统逻辑。 控制线连接到单元的锁存器的输出端子和耦合到可编程元件的解码逻辑，使得可编程元件可以通过串行扫描通过单元的控制信号进行编程。
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