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    METHOD OF MANUFACTURING SILICON CARBIDE SELF-ALIGNED EPITAXIAL MOSFET FOR HIGH POWERED DEVICE APPLICATIONS
    3.
    发明申请
    METHOD OF MANUFACTURING SILICON CARBIDE SELF-ALIGNED EPITAXIAL MOSFET FOR HIGH POWERED DEVICE APPLICATIONS 有权
    用于高功率器件应用的硅碳化物自对准外延MOSFET的制造方法

    公开(公告)号：US20100041195A1

    公开(公告)日：2010-02-18

    申请号：US12603603

    申请日：2009-10-22

    申请人： Christopher Harris ,  Kent Bertilsson ,  Andrei Konstantinov

    发明人： Christopher Harris ,  Kent Bertilsson ,  Andrei Konstantinov

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66068 ,  Y10S438/903 ,  Y10S438/969

    摘要： A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.

    摘要翻译： 自对准的碳化硅功率金属氧化物半导体场效应晶体管包括形成在第一层中的沟槽，其具有在沟槽内外延再生长的基极区域和源极区域。 通过源区域形成窗口，并且在沟槽的中间区域内形成窗口。 源极触点形成在与基极和源极区域接触的窗口内。 栅极氧化层形成在沟槽的周边区域和第一层的表面上的源极和基极区域上。 在沟槽的周边区域的基极区域上方的栅极氧化层上形成栅电极，在第一层的第二面上形成漏电极。

    Lateral Field Effect Transistor and Its Fabrication Comprising a Spacer Layer Above and Below the Channel Layer
    5.
    发明申请
    Lateral Field Effect Transistor and Its Fabrication Comprising a Spacer Layer Above and Below the Channel Layer 有权
    横向场效应晶体管及其制造包括通道层上方和下方的间隔层

    公开(公告)号：US20070262321A1

    公开(公告)日：2007-11-15

    申请号：US11661962

    申请日：2004-09-01

    申请人： Christopher Harris ,  Andrei Konstantinov

    发明人： Christopher Harris ,  Andrei Konstantinov

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/802 ,  H01L29/808 ,  H01L29/812

    摘要： A lateral field effect transistor for high switching frequencies having a source region layer (4) and a drain region layer (5) laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer (6) of lower doping concentration extending laterally and interconnecting the source region layer (4) and the drain region layer (5). The transistor has a gate electrode (7) arranged to control the properties of the channel layer (6), and a highly doped second-conductivity-type base layer (8) arranged under the channel layer (6) at least partially overlapping the gate electrode (7) and at a lateral distance to the drain region layer (5), the highly doped second-conductivity-type base layer (8) being shorted to the source region layer (4). The transistor also has at least one of the following: a) a spacer layer (10) having semiconductor material adjacent to the channel layer (6) and located between the channel layer (6) and gate electrode (7), at least in the vicinity of the gate electrode (7), and/or b) a spacer layer (9) having semiconductor material adjacent to the channel layer (6) and located between the channel layer (6) and the highly doped second-conductivity-type base layer (8).

    摘要翻译： 一种用于高开关频率的横向场效应晶体管，具有横向隔开的源区域层（4）和漏极区域层（5）以及高度掺杂的第一导电类型，具有较低掺杂浓度的第一导电型沟道层（6） 横向延伸并互连源区域层（4）和漏极区域层（5）。 晶体管具有布置成控制沟道层（6）的性质的栅电极（7），并且布置在沟道层（6）下方的高度掺杂的第二导电型基极层（8）至少部分地与栅极 电极（7），并且在与漏极区域（5）的横向距离处，高掺杂的第二导电型基极层（8）与源区域层（4）短路。 晶体管还具有以下至少一个：a）具有与沟道层（6）相邻并位于沟道层（6）和栅电极（7）之间的半导体材料的间隔层（10），至少在 栅极电极（7）的附近，和/或b）具有与沟道层（6）相邻并位于沟道层（6）和高度掺杂的第二导电型基底之间的半导体材料的间隔层（9） 层（8）。

    Lateral field effect transistor and its fabrication comprising a spacer layer above and below the channel layer
    6.
    发明授权
    Lateral field effect transistor and its fabrication comprising a spacer layer above and below the channel layer 有权
    横向场效应晶体管及其制造包括在沟道层上方和下方的间隔层

    公开(公告)号：US07834396B2

    公开(公告)日：2010-11-16

    申请号：US11661962

    申请日：2004-09-01

    申请人： Christopher Harris ,  Andrei Konstantinov

    发明人： Christopher Harris ,  Andrei Konstantinov

    IPC分类号： H01L29/94

    CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/802 ,  H01L29/808 ,  H01L29/812

    摘要： A lateral field effect transistor for high switching frequencies having a source region layer (4) and a drain region layer (5) laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer (6) of lower doping concentration extending laterally and interconnecting the source region layer (4) and the drain region layer (5). The transistor has a gate electrode (7) arranged to control the properties of the channel layer (6), and a second-conductivity-type base layer (8) arranged under the channel layer (6) at least partially overlapping the gate electrode (7) and at a lateral distance to the drain region layer (5), the highly doped second-conductivity-type base layer (8) being shorted to the source region layer (4). The transistor also has at least one of the following: a) a spacer layer (10) having semiconductor material adjacent to the channel layer (6) and located between the channel layer (6) and gate electrode (7), at least in the vicinity of the gate electrode (7), and/or b) a spacer layer (9) having semiconductor material adjacent to the channel layer (6) and located between the channel layer (6) and the second-conductivity-type base layer (8).

    摘要翻译： 一种用于高开关频率的横向场效应晶体管，具有横向隔开的源区域层（4）和漏极区域层（5）以及高度掺杂的第一导电类型，具有较低掺杂浓度的第一导电型沟道层（6） 横向延伸并互连源区域层（4）和漏极区域层（5）。 晶体管具有布置成控制沟道层（6）的性质的栅电极（7）和布置在通道层（6）下方的至少部分地与栅电极重叠的第二导电型基极层（8） 如图7所示，并且在与漏极区域（5）的横向距离处，高掺杂的第二导电型基极层（8）被短路到源极区域层（4）。 晶体管还具有以下至少一个：a）具有与沟道层（6）相邻并位于沟道层（6）和栅电极（7）之间的半导体材料的间隔层（10），至少在 栅极电极（7）的附近，和/或b）具有与沟道层（6）相邻并位于沟道层（6）和第二导电型基极层（6）之间的半导体材料的间隔层（9） 8）。

    Method of manufacturing a vertical junction field effect transistor having an epitaxial gate
    8.
    发明授权
    Method of manufacturing a vertical junction field effect transistor having an epitaxial gate 有权
    制造具有外延栅的垂直结型场效应晶体管的方法

    公开(公告)号：US07279368B2

    公开(公告)日：2007-10-09

    申请号：US11071454

    申请日：2005-03-04

    申请人： Christopher Harris ,  Andrei Konstantinov ,  Cem Basceri

    发明人： Christopher Harris ,  Andrei Konstantinov ,  Cem Basceri

    IPC分类号： H01L21/332

    CPC分类号： H01L29/8083 ,  H01L29/1066 ,  H01L29/1608

    摘要： A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is formed within the trench by epitaxial regrowth. The epitaxial gate structure may include separate first and second epitaxial gate layers, and may have either a graded or uniform dopant concentration profile.

    摘要翻译： 垂直结场效应晶体管包括形成在外延层中的沟槽。 沟槽围绕外延层的沟道区。 沟道区可以具有渐变或均匀的掺杂浓度分布。 通过外延再生长在沟槽内形成外延栅极结构。 外延栅结构可以包括单独的第一和第二外延栅层，并且可以具有渐变的或均匀的掺杂剂浓度分布。

    Method of manufacturing a vertical junction field effect transistor having an epitaxial gate
    9.
    发明申请
    Method of manufacturing a vertical junction field effect transistor having an epitaxial gate 有权
    制造具有外延栅的垂直结型场效应晶体管的方法

    公开(公告)号：US20060199312A1

    公开(公告)日：2006-09-07

    申请号：US11071454

    申请日：2005-03-04

    申请人： Christopher Harris ,  Andrei Konstantinov ,  Cem Basceri

    发明人： Christopher Harris ,  Andrei Konstantinov ,  Cem Basceri

    IPC分类号： H01L21/332 ,  H01L21/337

    CPC分类号： H01L29/8083 ,  H01L29/1066 ,  H01L29/1608

    摘要： A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is formed within the trench by epitaxial regrowth. The epitaxial gate structure may include separate first and second epitaxial gate layers, and may have either a graded or uniform dopant concentration profile.

    摘要翻译： 垂直结场效应晶体管包括形成在外延层中的沟槽。 沟槽围绕外延层的沟道区。 沟道区可以具有渐变或均匀的掺杂浓度分布。 通过外延再生长在沟槽内形成外延栅极结构。 外延栅结构可以包括单独的第一和第二外延栅层，并且可以具有渐变的或均匀的掺杂剂浓度分布。

    Method of producing a semiconductor device of SiC
    10.
    发明授权
    Method of producing a semiconductor device of SiC 有权
    制造SiC半导体器件的方法

    公开(公告)号：US06306773B1

    公开(公告)日：2001-10-23

    申请号：US09496085

    申请日：2000-02-01

    申请人： Christian Adås ,  Stefan Karlsson ,  Andrei Konstantinov ,  Christopher Harris ,  Thomas Hörman

    发明人： Christian Adås ,  Stefan Karlsson ,  Andrei Konstantinov ,  Christopher Harris ,  Thomas Hörman

    IPC分类号： H01L21302

    CPC分类号： B81C1/00595 ,  B81C2201/0114 ,  B81C2201/0133 ,  H01L21/0475

    摘要： The invention relates to a method for selective etching of SiC, the etching being carried out by applying a positive potential to a layer (3; 8) of p-type SiC being in contact with an etching solution containing fluorine ions and having an oxidising effect on SiC. The invention also relates to a method for producing a SiC micro structure having free hanging parts (i.e. diaphragm, cantilever or beam) on a SiC-substrate, a method for producing a MEMS device of SiC having a free hanging structure, and a method for producing a piezo-resistive pressure sensor comprising the step of applying a positive potential to a layer (8) of p-type SiC being in contact with an etching solution containing fluorine ions and having an oxidising effect on SiC.

    摘要翻译： 本发明涉及一种选择性蚀刻SiC的方法，该蚀刻是通过向与含有氟离子的蚀刻溶液接触并具有氧化效应的p型SiC层（3; 8）施加正电位而进行的 在SiC上。 本发明还涉及一种用于制造在SiC衬底上具有自由悬挂部分（即隔膜，悬臂或梁）的SiC微结构的方法，用于制造具有自由悬挂结构的SiC的MEMS器件的方法，以及用于 制造压阻式压力传感器，包括向与所述氟离子的蚀刻溶液接触并对SiC具有氧化作用的p型SiC层（8）施加正电位的步骤。