公开(公告)号：US5673130A

公开(公告)日：1997-09-30

申请号：US582841

申请日：1996-01-02

申请人： Ray D. Sundstrom ,  Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

发明人： Ray D. Sundstrom ,  Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

IPC分类号： H03M5/04 ,  H04B10/02 ,  H04B10/12 ,  H04B10/18 ,  H04L7/00 ,  H04L25/06 ,  H04L25/49 ,  H04B10/00

CPC分类号： H04B10/516 ,  H04L25/062 ,  H04L7/0008 ,  H04L7/0075

摘要： A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.

摘要翻译： 数据发送器（12）将并行数据作为光脉冲发送在多个光通道（14）上。 数据接收器（16）将光脉冲转换回电压电平，并将电压电平与参考电容器电压（42）进行比较。 在检测逻辑和逻辑零时，电容电压应保持适当的噪声容限的中档值。 任何长串连续的逻辑或零都会使电容器电压与数据电压相同的电平进行充放电，从而导致数据错误。 为了防止数据错误，通过反转某些位来对数据进行编码（18）以分解长序列的连续逻辑状态。 编码信息作为发送时钟通过另一个光纤信道被发送到数据接收器。 检索解码信息（20），使得编码数据可被转换回适当的逻辑状态。

公开(公告)号：US5394108A

公开(公告)日：1995-02-28

申请号：US937034

申请日：1992-08-31

申请人： Christopher K. Y. Chun ,  Ray D. Sundstrom

发明人： Christopher K. Y. Chun ,  Ray D. Sundstrom

IPC分类号： H04L25/02 ,  H03K3/287 ,  H04B10/158 ,  G06G7/18

CPC分类号： H04B10/6931 ,  H03K3/287

摘要： Binary current signals are differentiated to produce pulses indicative of the front and rear edges. The pulses are amplified and utilized in a latch to regenerate binary voltage signals which are amplified replicas of the input signals. Because of the input differentiator the sensitivity of the circuit remains high while the latched output makes the circuit burst mode ready.

摘要翻译： 二进制电流信号被微分以产生指示前边缘和后边缘的脉冲。 脉冲被放大并用于锁存器中以再生二进制电压信号，这是输入信号的放大副本。 由于输入微分器，电路的灵敏度保持高电平，而锁存的输出使电路突发模式准备就绪。

公开(公告)号：US5781129A

公开(公告)日：1998-07-14

申请号：US811062

申请日：1997-03-03

申请人： Daniel B. Schwartz ,  Ray D. Sundstrom

发明人： Daniel B. Schwartz ,  Ray D. Sundstrom

IPC分类号： H03M5/14 ,  H03M7/00

CPC分类号： H03M5/145

摘要： An adaptive encoder (10) provides a fixed upper limit on the number of consecutively transmitted data bits at a particular data bit location of a data word having a common logic value. A coder circuit (44) provides prioritization for a storage comparator register (102) to determine when data in a data channel (32) should be complemented. An invert circuit (58) complements the data in the data channel (32) when an upper limit of consecutive transmitted data bits have common logic values.

摘要翻译： 自适应编码器（10）在具有公共逻辑值的数据字的特定数据位位置上提供连续发送的数据位的数量的固定上限。 编码器电路（44）为存储比较器寄存器（102）提供优先级以确定数据信道（32）中的数据何时应被补充。 当连续发送的数据位的上限具有公共逻辑值时，反相电路（58）补充数据信道（32）中的数据。

公开(公告)号：US4994690A

公开(公告)日：1991-02-19

申请号：US471581

申请日：1990-01-29

申请人： Ray D. Sundstrom ,  Cleon Petty ,  Dwight D. Esgar

发明人： Ray D. Sundstrom ,  Cleon Petty ,  Dwight D. Esgar

IPC分类号： G06F13/36 ,  G06F13/40 ,  H04L12/40 ,  H04L25/02

CPC分类号： H04L25/0272 ,  G06F13/4072 ,  H04L12/40 ,  H04L25/0298

摘要： A split level differential bus having first and second signals at first and second lines, respectively, for transmitting data from a typical driver to a typical receiver, includes a first independent voltage source for terminating the first line and a second independent voltage source for terminating the second line, the second independent voltage source providing a voltage level that is different from the voltage level provided by the first independent voltage source. A current switch circuit controlled by the driver for switching current from the first line to the second line. A level shifting circuit coupled between the first line and the receiver for level shifting the first signal by a predetermined voltage.

公开(公告)号：US4980581A

公开(公告)日：1990-12-25

申请号：US526267

申请日：1990-05-21

申请人： Dwight D. Esgar ,  Ray D. Sundstrom

发明人： Dwight D. Esgar ,  Ray D. Sundstrom

IPC分类号： H03K19/0175 ,  H03K3/2893 ,  H03K5/24 ,  H03K19/086

CPC分类号： H03K3/2893 ,  H03K5/2418

摘要： A circuit having first and second inputs and first and second outputs includes a differential receiver circuit responsive to the first and second inputs for providing corresponding output logic signals at the first and second outputs. A tri-state detection circuit responsive to the first and second inputs and having an output for providing a first predetermined voltage to the differential receiver circuit when the first and second inputs are in a normal mode and for providing an increased second predetermined voltage to the differential receiver circuit when the first and second inputs are in a tri-state mode wherein oscillation of the differential receiver circuit is prevented and the outputs are forced to known logic states while the noise margin of the differential receiver is increased without a sacrifice in common mode range.

摘要翻译： 具有第一和第二输入以及第一和第二输出的电路包括响应于第一和第二输入的差分接收器电路，用于在第一和第二输出处提供对应的输出逻辑信号。 一种三态检测电路，其响应于第一和第二输入，并且具有用于当第一和第二输入处于正常模式时向差分接收器电路提供第一预定电压的输出，并且用于向差分提供增加的第二预定电压 当第一和第二输入处于三态模式时，其中防止差分接收器电路的振荡，并且将输出强制为已知的逻辑状态，同时增加差分接收器的噪声容限而不牺牲共模范围 。

公开(公告)号：US5391945A

公开(公告)日：1995-02-21

申请号：US125729

申请日：1993-09-24

申请人： C. Christopher Hanke ,  Todd Pearson ,  Ray D. Sundstrom

发明人： C. Christopher Hanke ,  Todd Pearson ,  Ray D. Sundstrom

IPC分类号： H03K19/003 ,  H03K19/088 ,  H03K19/0175 ,  H03K19/092

CPC分类号： H03K19/00323

摘要： A circuit and method for providing phase synchronization between an ECL output signal and a TTL or CMOS output signal has been provided. The circuit includes phase locked loops (20, 24) to make the difference of delays through an ECL-TTL/CMOS translation path with that of a straight ECL path irrelevant. As a result, in order to achieve phase synchronization between an ECL signal and a TTL/CMOS signal, one only needs to match the propagation delay of a delay component (22) to that of a TTL/CMOS-ECL translator (26) as opposed to a delay component and an ECL-TTL/CMOS translator.

摘要翻译： 已经提供了一种用于在ECL输出信号和TTL或CMOS输出信号之间提供相位同步的电路和方法。 该电路包括锁相环（20,24），以使通过ECL-TTL / CMOS平移路径的延迟差与直线ECL路径的差异不相关。 结果，为了实现ECL信号和TTL / CMOS信号之间的相位同步，仅需要将延迟部件（22）的传播延迟与TTL / CMOS-ECL转换器（26）的传播延迟相匹配，作为 与延迟部件和ECL-TTL / CMOS转换器相反。

公开(公告)号：US4998029A

公开(公告)日：1991-03-05

申请号：US374722

申请日：1989-07-03

申请人： Ray D. Sundstrom

发明人： Ray D. Sundstrom

IPC分类号： G05F1/10 ,  H03K19/003 ,  H03K19/018

CPC分类号： H03K19/01812 ,  H03K19/00353

摘要： An ECL to TTL translator converts a signal from ECL logic levels to TTL compatible logic levels without introducing current spikes in the output signal during logic translations. The ECL input signal is transformed into first and second differentially related currents which develop first and second voltages for biasing first and second switching circuits which in turn generate first and second complementary control signals. The sum total of the differentially related currents are limited to a predetermined magnitude blocking simultaneously assertion of the control signals. An output stage includes an upper and lower transistors each responsive to the first and second control signal respectively for developing a TTL high and TTL low output signal. The first and second switching circuits inhibit simultaneous conduction of the upper and lower transistors of the output stage preventing undesirable current spikes in the output signal thereof.

公开(公告)号：US5444395A

公开(公告)日：1995-08-22

申请号：US161559

申请日：1993-12-06

申请人： Dwight D. Esgar ,  Ray D. Sundstrom ,  Phuc C. Pham

发明人： Dwight D. Esgar ,  Ray D. Sundstrom ,  Phuc C. Pham

IPC分类号： H03K17/0422 ,  H03K19/013 ,  H03K19/018 ,  H03K19/0175 ,  H03K17/04

CPC分类号： H03K19/01812 ,  H03K17/0422 ,  H03K19/013

摘要： A non-saturating transistor circuit (11) having a first terminal (13), a control terminal (12), and a second terminal (14). The first terminal (13), control terminal (12), and second terminal (14) correspond respectively to a collector, base, and emitter of a transistor. The non-saturating transistor circuit (11) comprises a voltage divider (15), a diode (19), and a transistor (16). The voltage divider (15) enables the transistor (16) when a voltage is applied across the control terminal (12) and the second terminal (14) of non-saturating transistor circuit (11). The diode (19) removes current drive to the transistor (16) prior to the transistor (16) becoming saturated thus preventing the transistor (16) from saturating under all operating conditions.

摘要翻译： 具有第一端子（13），控制端子（12）和第二端子（14）的非饱和晶体管电路（11）。 第一端子（13），控制端子（12）和第二端子（14）分别对应于晶体管的集电极，基极和发射极。 非饱和晶体管电路（11）包括分压器（15），二极管（19）和晶体管（16）。 当跨越控制端子（12）和非饱和晶体管电路（11）的第二端子（14）施加电压时，分压器（15）使得晶体管（16）能够被施加。 在晶体管（16）饱和之前，二极管（19）去除对晶体管（16）的电流驱动，从而防止晶体管（16）在所有工作条件下饱和。

公开(公告)号：US5434523A

公开(公告)日：1995-07-18

申请号：US223186

申请日：1994-04-05

申请人： Ray D. Sundstrom

发明人： Ray D. Sundstrom

IPC分类号： H03K5/13 ,  H03K3/017 ,  H03K3/66 ,  H03K5/156 ,  H03K9/08

CPC分类号： H03K5/1565 ,  H03K9/08

摘要： The present invention provides an output signal whose pulse width may be adjusted with respect to the pulse width of an incoming input signal. In particular, a plurality of signals is generated in response to the input signal. One of the plurality of signals is selected for controlling when the output signal transitions from a first logic state to a second logic state, and one of the plurality of signals is selected for controlling when the output signal transitions from a second logic state to a first logic state wherein the output signal has a pulse width being a function of the selection of the plurality of signals.

摘要翻译： 本发明提供一种输出信号，其脉冲宽度可以相对于输入输入信号的脉冲宽度进行调节。 特别地，响应于输入信号产生多个信号。 选择多个信号中的一个用于控制何时输出信号从第一逻辑状态转换到第二逻辑状态，并且选择多个信号中的一个用于控制何时输出信号从第二逻辑状态转换到第一逻辑状态 逻辑状态，其中所述输出信号具有作为所述多个信号的选择的函数的脉冲宽度。

公开(公告)号：US5230013A

公开(公告)日：1993-07-20

申请号：US864247

申请日：1992-04-06

申请人： C. Christopher Hanke ,  Ray D. Sundstrom

发明人： C. Christopher Hanke ,  Ray D. Sundstrom

IPC分类号： H03K5/15 ,  H03L7/18

CPC分类号： H03L7/18 ,  H03K5/15066

摘要： A circuit for generating precise, phase shifted, CMOS level output signals with respect to an input data signal has been provided. The circuit utilizes a phase-locked loop for generating a precise clock signal. This precise clock signal is then utilized to clock a plurality of serially-coupled flip-flops wherein two-times the input data signal is applied to the data input of the first serially-coupled flip-flop. The outputs of the serially-coupled flip-flops are ECL signals which are then translated to CMOS level signals via ECL-CMOS translators. Finally, the output signals of the translators are respectively used to clock divide-by-two configured flip-flops in order to provide the plurality of precise, phase shifted CMOS output signals. The plurality of precise, phase shifted, CMOS output signals have a 50% duty cycle and represent phase shifted versions of the input data signal wherein the minimum time delay between signals is substantially equal to the period of the precise clock signal.

摘要翻译： 已经提供了一种用于相对于输入数据信号产生精确的相移CMOS电平输出信号的电路。 该电路利用锁相环产生精确的时钟信号。 这个精确的时钟信号随后用于对多个串联耦合的触发器进行时钟，其中输入数据信号的两倍被施加到第一串联耦合触发器的数据输入端。 串联耦合触发器的输出是ECL信号，然后通过ECL-CMOS转换器将其转换为CMOS电平信号。 最后，翻译器的输出信号分别用于对二分之一配置的触发器进行时钟钟，以提供多个精确的相移CMOS输出信号。 多个精确的相移CMOS输出信号具有50％的占空比并且表示输入数据信号的相移版本，其中信号之间的最小时间延迟基本上等于精确时钟信号的周期。