公开(公告)号：US06365523B1

公开(公告)日：2002-04-02

申请号：US09177188

申请日：1998-10-22

申请人： Syun-Ming Jang ,  Chu-Yun Fu ,  Ying-Ho Chen

发明人： Syun-Ming Jang ,  Chu-Yun Fu ,  Ying-Ho Chen

IPC分类号： H01L21302

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  H01L21/31612

摘要： A method for forming a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer employed within a microelectronics fabrication. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths and the series of mesas is separated by a series of apertures. There is then formed upon the topographic substrate layer a blanket first aperture fill layer. The blanket first aperture fill layer is formed employing a first simultaneous deposition and sputter method. The blanket first aperture fill layer fills the series of apertures to a planarizing thickness at least as high as the height of the mesas while simultaneously forming a series of protrusions of the blanket first aperture fill layer corresponding with the series of mesas, where the thickness of a protrusion of the blanket first aperture fill layer over a narrow mesa is less than the thickness of a protrusion of the blanket first aperture fill layer over a wide mesa. The first simultaneous deposition and sputter method employs a first deposition rate:sputter rate ratio which provides sufficient thickness of the blanket first aperture fill layer over the narrow mesa such that upon chemical mechanical polish (CMP) planarizing the blanket first aperture fill layer to form a series of patterned planarized first aperture fill layers within the series of apertures erosion of the narrow mesa is attenuated. Finally, there is then chemical mechanical polish (CMP) planarized the blanket first aperture fill layer to form the series of patterned planarized first aperture fill layers within the series of apertures.

摘要翻译： 一种用于在微电子学制造中使用的地形衬底层内的一系列孔内形成一系列图案化的平坦化孔填充层的方法。 首先提供了在微电子制造中使用的地形衬底层，其中地形衬底层包括基本上等同的高度但具有不同宽度的一系列台面，并且一系列台面由一系列孔分隔开。 然后在地形衬底层上形成毯子第一孔填充层。 毯子第一孔填充层使用第一同时沉积和溅射方法形成。 毯子第一孔填充层将一系列孔填充至至少与台面的高度相同的平坦化厚度，同时形成与一系列台面相对应的毯子第一孔填充层的一系列突起，其中厚度 毯子第一孔填充层在窄台面上的突起小于宽台面上的第一孔填充层的突起的厚度。 第一同时沉积和溅射方法使用第一沉积速率：溅射速率比，其在窄台面上提供足够厚度的第一孔填充层，使得在化学机械抛光（CMP）上平坦化第一孔填充层以形成 一系列图案化的平面化的第一孔径填充层在一系列孔径内的狭窄台面的侵蚀被衰减。 最后，然后是化学机械抛光（CMP）平坦化第一孔填充层，以在一系列孔内形成一系列图案化的平坦化的第一孔填充层。

公开(公告)号：US20060211250A1

公开(公告)日：2006-09-21

申请号：US11082517

申请日：2005-03-17

申请人： Chuang-Ping Hou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Chu-Yun Fu ,  Tung-Ching Tseng

发明人： Chuang-Ping Hou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Chu-Yun Fu ,  Tung-Ching Tseng

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L21/31053

摘要： A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.

摘要翻译： 提供了一种利用化学机械抛光（CMP）工艺形成半导体器件的方法。 在一个示例中，该方法包括依次执行第一CMP处理，以使用高选择性浆料（HSS）和第一抛光垫去除半导体器件的氧化物表面的第一部分，中断第一CMP工艺，清洁半导体器件 和第一抛光垫，并且执行用于去除氧化物表面的第二部分的第二CMP工艺。

公开(公告)号：US06261957B1

公开(公告)日：2001-07-17

申请号：US09378496

申请日：1999-08-20

申请人： Syun-Ming Jang ,  Chu-Yun Fu

发明人： Syun-Ming Jang ,  Chu-Yun Fu

IPC分类号： H01L2100

CPC分类号： H01L21/76229

摘要： Within a method for forming an aperture fill layer within an aperture there is first provided a topographic substrate which has formed therein a pair of mesas which defines an aperture. There is then formed over the topographic substrate and into the aperture a blanket aperture fill layer while employing a high density plasma chemical vapor deposition (HDP-CVD) method, where the blanket aperture fill layer is formed to a thickness greater than a depth of the aperture while forming a pair of protrusions over the pair of mesas. There is then etched, while employing a sputter etch method, the blanket aperture fill layer to form an etched blanket aperture fill layer such that the pair of protrusions of the blanket aperture fill layer formed over the pair of mesas is etched more rapidly than a portion of the blanket aperture fill layer formed within the aperture. Finally, there is then chemical mechanical polish (CMP) planarized the etched blanket aperture fill layer to form a patterned planarized aperture fill layer within the aperture while removing the pair of protrusions form over the pair of mesas. The method may be employed to form with enhanced planarity and attenuated residue formation a trench isolation region within an isolation trench within a semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication.

摘要翻译： 在用于在孔内形成孔填充层的方法中，首先提供了形成有一对限定孔径的台面的地形衬底。 然后，在使用高密度等离子体化学气相沉积（HDP-CVD）方法的同时，在地形衬底上形成覆盖孔隙填充层，并在孔中形成覆盖孔填充层，其中覆盖孔填充层形成厚度大于 同时在所述一对台面上形成一对突起。 然后，在采用溅射蚀刻方法的同时，将橡皮布孔填充层蚀刻，以形成蚀刻的橡皮布孔隙填充层，使得形成在该对台面上方的橡皮布孔填充层的一对突起比一部分 形成在孔内的橡皮布孔填充层。 最后，化学机械抛光（CMP）将蚀刻的橡皮布孔填充层平坦化，以在孔内形成图案化的平坦化孔填充层，同时从一对台面上移除一对突起。 该方法可用于在半导体集成电路微电子制造中使用的半导体衬底内的隔离沟槽内的沟槽隔离区域内以增强的平面性和衰减的残留物形成形成。

公开(公告)号：US06228780B1

公开(公告)日：2001-05-08

申请号：US09318957

申请日：1999-05-26

申请人： So-Wein Kuo ,  Chu-Yun Fu ,  Syun-Ming Jang ,  Ruey-Lian Hwang

发明人： So-Wein Kuo ,  Chu-Yun Fu ,  Syun-Ming Jang ,  Ruey-Lian Hwang

IPC分类号： H01L2131

CPC分类号： H01L28/40 ,  H01L21/3185 ,  H01L28/56 ,  Y10S438/958

摘要： A new method of forming a non-shrinkable metal passivation layer that will eliminate metal voiding and improve electromigration lifetime of the integrated circuit device is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered by an insulating layer. A metal layer is deposited overlying the insulating layer and patterned to form metal lines wherein there is a gap between two of the metal lines. A non-shrinkable passivation layer is formed according to the following steps: 1) a HDP-CVD oxide layer is deposited overlying the metal lines wherein the gap is filled by the HDP-CVD oxide layer. 2) A silicon nitride layer is deposited by plasma-enhanced chemical vapor deposition overlying the HDP-CVD oxide layer. Or, 1) a PECVD oxide layer is deposited over the metal lines. 2) A silicon nitride layer is deposited by PECVD over the oxide layer to fill the gap and complete the passivation. Then, the fabrication of the integrated circuit device is completed. Completion of fabrication includes thermal processing. Voids are not formed within the metal lines because the non-shrinkable passivation layer does not shrink during the thermal processing.

摘要翻译： 描述了一种形成不会收缩的金属钝化层的新方法，其将消除金属空隙并提高集成电路器件的电迁移寿命。 半导体器件结构设置在半导体衬底中并在半导体衬底上并被绝缘层覆盖。 沉积在绝缘层上的金属层被图案化以形成金属线，其中在两条金属线之间存在间隙。 根据以下步骤形成不可收缩的钝化层：1）将HDP-CVD氧化物层沉积在金属线上，其中间隙由HDP-CVD氧化物层填充。 2）通过覆盖HDP-CVD氧化物层的等离子体增强化学气相沉积沉积氮化硅层。 或者，1）在金属线上沉积PECVD氧化物层。 2）通过PECVD在氧化物层上沉积氮化硅层以填充间隙并完成钝化。 然后，完成集成电路装置的制造。 制造完成包括热处理。 由于在热处理期间不可收缩的钝化层不收缩，所以在金属线内不形成空隙。

公开(公告)号：US06479385B1

公开(公告)日：2002-11-12

申请号：US09583397

申请日：2000-05-31

申请人： Syun-Ming Jang ,  Chu-Yun Fu

发明人： Syun-Ming Jang ,  Chu-Yun Fu

IPC分类号： H01L21302

CPC分类号： H01L21/02238 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76837

摘要： A process for forming a composite, interlevel dielectric, (ILD), layer, for MOSFET devices, has been developed. The composite ILD layer is comprised with an underlying, undoped silicon glass layer, providing the material needed to fill the narrow spaces between polysilicon gate structures of the MOSFET devices. A P2O5 doped, insulator layer, is next formed on the underlying, undoped silicon glass layer, to provide a mobile ion gettering property. An overlying, undoped silicon glass layer is then deposited and subjected to a chemical mechanical polishing procedure, resulting in the desired planar top surface topography, for the composite ILD layer.

摘要翻译： 已经开发了用于形成MOSFET器件的复合层间电介质（ILD）层的工艺。 复合ILD层包含底层的未掺杂的硅玻璃层，提供填充MOSFET器件的多晶硅栅极结构之间的狭窄空间所需的材料。 随后在下面未掺杂的硅玻璃层上形成P2O5掺杂的绝缘体层，以提供移动离子吸杂性质。 然后沉积覆盖的未掺杂的硅玻璃层，并进行化学机械抛光程序，得到复合ILD层所需的平面顶表面形貌。

公开(公告)号：US06245682B1

公开(公告)日：2001-06-12

申请号：US09266374

申请日：1999-03-11

申请人： Chu-Yun Fu ,  Syun-Ming Jang

发明人： Chu-Yun Fu ,  Syun-Ming Jang

IPC分类号： H01L21311

CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/3145 ,  Y10S438/952

摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for forming and then later removing a silicon oxynitride, SiON, anti-reflection coating (ARC) over a semiconductor substrate, for the purpose of enhancing the resolution of photolithographically defined sub-micron polysilicon gates. The problem addressed by this invention is that the SiON ARC must first be used to reduce optical reflection from a blanket polysilicon surface, during the photolithography exposure step that defines the sub-micron polysilicon gate features, and then the ARC must be removed by a wet etch process that will not chemically attack the gate oxide under the polysilicon gate features or any exposed polysilicon surfaces. This is accomplished with a fabrication method that uses hot phosphoric acid (H3PO4) to preferentially etch the SiON ARC, relative to the thermal gate oxide, while also using thin thermal oxide layers to protect the polysilicon gate surfaces from being severely attacked by the hot H3PO4. This new method also features the ability to tailor the combination of the composition and thickness of the SiON layer and the thickness of the underlying protective thin thermal oxide layer, in order to minimize the undesired high optical reflectivity of the underlying polysilicon surface.

摘要翻译： 本发明涉及集成电路器件的制造，更具体地说，涉及一种用于在半导体衬底上形成并随后去除氧氮化硅SiON，抗反射涂层（ARC）的方法，用于增强光刻定义的分辨率 亚微米多晶硅门。 本发明解决的问题是，在限定亚微米多晶硅栅极特征的光刻曝光步骤期间，必须首先使用SiON ARC来减少来自覆盖多晶硅表面的光学反射，然后必须通过湿法去除ARC 不会在多晶硅栅极特征或任何暴露的多晶硅表面下化学侵蚀栅极氧化物的蚀刻工艺。 这是通过使用热磷酸（H 3 PO 4）相对于热栅氧化物优先蚀刻SiON ARC的制造方法实现的，同时还使用薄的热氧化物层来保护多晶硅栅极表面免受热H3PO4的严重攻击 。 这种新方法还具有能够定制SiON层的组成和厚度以及下面的保护性薄热氧化物层的厚度的组合，以便使底层多晶硅表面的不期望的高光学反射率最小化。

公开(公告)号：US06207483B1

公开(公告)日：2001-03-27

申请号：US09527183

申请日：2000-03-17

申请人： Chu-Yun Fu ,  Chung-Long Chang ,  Syun-Ming Jang ,  Shwangming Jeng

发明人： Chu-Yun Fu ,  Chung-Long Chang ,  Syun-Ming Jang ,  Shwangming Jeng

IPC分类号： H01L218238

CPC分类号： H01L21/823828 ,  H01L21/28035 ,  H01L21/32115

摘要： There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.

摘要翻译： 提供了一种用于平滑CMOS结构的未掺杂多晶硅区域的表面的方法，主要是栅极区域。 使用直接HPD-CVD氩溅射将表面粗糙度提高了50％以上。 氩等离子体溅射可以单独使用或与氧化物，氮化物或氮氧化物的薄覆盖层结合使用。 与使用常规制造工艺制造的器件相比，使用该工艺制造的器件表现出优异的电气特性和改进的可靠性。

公开(公告)号：US6090714A

公开(公告)日：2000-07-18

申请号：US177189

申请日：1998-10-23

申请人： Syun-Ming Jang ,  Chu-Yun Fu

发明人： Syun-Ming Jang ,  Chu-Yun Fu

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/76229 ,  H01L21/31055 ,  H01L21/31608

摘要： A method for forming a planarized trench fill layer within a trench within a substrate. There is first provided a substrate having a trench formed therein. There is then formed over the substrate and at least partially filling the trench a first trench fill layer formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. There is then formed upon the first trench fill layer a second trench fill layer formed employing a subatmospheric pressure thermal chemical vapor deposition (SACVD) method employing ozone as an oxidant source material and tetraethylorthosilicate (TEOS) as a silicon source material. Finally, there is then planarized by employing a chemical mechanical polish (CMP) planarizing method the second trench fill layer and the first trench fill layer to form a patterned planarized trench fill layer within the trench. When employing the method, the first trench fill layer is formed to a first thickness and the second trench fill layer is formed to a second thickness, where the first thickness and the second thickness are chosen such that there is attenuated erosion of the substrate when forming the patterned planarized trench fill layer within the trench while employing the chemical mechanical polish (CMP) planarizing method. The method is particularly useful for forming patterned planarized trench fill dielectric layers within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications.

摘要翻译： 一种用于在衬底内的沟槽内形成平坦化的沟槽填充层的方法。 首先提供其中形成有沟槽的衬底。 然后在衬底上形成并且至少部分地填充沟槽，使用高密度等离子体化学气相沉积（HDP-CVD）方法形成的第一沟槽填充层。 然后在第一沟槽填充层上形成第二沟槽填充层，该第二沟槽填充层采用使用臭氧作为氧化剂源材料和四乙基原硅酸盐（TEOS）作为硅源材料的低于大气压的热化学气相沉积（SACVD）方法。 最后，然后通过采用化学机械抛光（CMP）平面化方法平面化第二沟槽填充层和第一沟槽填充层，以在沟槽内形成图案化的平坦化沟槽填充层。 当采用该方法时，第一沟槽填充层被形成为第一厚度，并且第二沟槽填充层被形成为第二厚度，其中第一厚度和第二厚度被选择为使得当形成时基板受到衰减的侵蚀 在使用化学机械抛光（CMP）平面化方法的同时，在沟槽内形成图案化的平坦化沟槽填充层。 该方法对于在半导体集成电路微电子器件制造中使用的半导体衬底内的隔离沟槽内形成图案化的平坦化沟槽填充电介质层特别有用。

公开(公告)号：US6037018A

公开(公告)日：2000-03-14

申请号：US108866

申请日：1998-07-01

申请人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

发明人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

IPC分类号： C23C16/40 ,  H01L21/762 ,  B05D3/06 ,  H01L21/76

CPC分类号： H01L21/76232 ,  C23C16/402

摘要： A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O.sub.3 -TEOS protective liner 40. The O.sub.3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O.sub.3 -TEOS layer has novel process temperature (400 to 560.degree. C.) and low pressure (40 to 80 torr) that allows the O.sub.3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O.sub.3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.

摘要翻译： 用HDPCVD氧化物50填充浅沟槽28的方法。本发明具有两个衬垫：（a）热氧化物衬垫36和（b）上覆的共形O3-TEOS保护衬垫40.O3-TEOS保护衬垫40防止 HDPCVD氧化物50从溅射破坏沟槽侧壁和掩模层24.O3-TEOS层具有新的工艺温度（400至560℃）和低压（40至80托），允许O 3 -TEOS层沉积 该方法开始于在衬底上形成衬垫氧化物层20和阻挡层24。 沟槽28通过衬垫氧化物层20和阻挡层24形成在衬底10中。热氧化物衬里36和保护性O 3 -TEOS衬里层40形成在沟槽28的壁上并且在阻挡层24上方 最后，在填充沟槽28的保护衬垫层40之上形成高密度等离子体化学气相沉积（HDPCVD）氧化物层50。

公开(公告)号：US20050095727A1

公开(公告)日：2005-05-05

申请号：US10701824

申请日：2003-11-05

申请人： Weng Chang ,  Chih-Cheng Lu ,  Chu-Yun Fu ,  Syun-Ming Jang

发明人： Weng Chang ,  Chih-Cheng Lu ,  Chu-Yun Fu ,  Syun-Ming Jang

IPC分类号： H01L21/762 ,  H01L23/544 ,  H01L21/66 ,  G01R31/26 ,  H01L21/76

CPC分类号： H01L22/34 ,  H01L21/76229

摘要： A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 公开了一种用于测试浅沟槽隔离间隙填充特性的测试区域布局。 每个测试区域还包括设置在测试区域的内部部分中的至少一个测试图案。 在优选实施例中，测试图案是相对于彼此不连续的正方形或更优选的两个直径相对的“L”形。 要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。