公开(公告)号：US08878338B2

公开(公告)日：2014-11-04

申请号：US13485340

申请日：2012-05-31

申请人： Chun Hua Chang ,  Der-Chyang Yeh ,  Kuang-Wei Cheng ,  Yuan-Hung Liu ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng

发明人： Chun Hua Chang ,  Der-Chyang Yeh ,  Kuang-Wei Cheng ,  Yuan-Hung Liu ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC分类号： H01L29/00 ,  H01L21/02 ,  H01L29/02

CPC分类号： H01L28/40 ,  H01L21/02 ,  H01L21/768 ,  H01L23/147 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/53295 ,  H01L28/60 ,  H01L29/02 ,  H01L2924/0002 ,  H01L2924/00

摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.

摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在插入器中形成通孔，并且在下层金属化层和较高级金属化层之间形成电容器。 电容器可以是例如具有双电容器电介质层的平面电容器。

公开(公告)号：US08765549B2

公开(公告)日：2014-07-01

申请号：US13458476

申请日：2012-04-27

申请人： Chun Hua Chang ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Wen-Chih Chiou

发明人： Chun Hua Chang ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Wen-Chih Chiou

IPC分类号： H01L21/8242

CPC分类号： H01L23/642 ,  H01L23/49822 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.

摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在一个实施例中，在通孔和下层金属化层之间形成电容器。 电容器可以是例如形成在衬底上或形成在衬底上的电介质层上的平面电容器。

公开(公告)号：US20130285200A1

公开(公告)日：2013-10-31

申请号：US13458476

申请日：2012-04-27

申请人： Chun Hua Chang ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Wen-Chih Chiou

发明人： Chun Hua Chang ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Wen-Chih Chiou

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L23/642 ,  H01L23/49822 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.

摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在一个实施例中，在通孔和下层金属化层之间形成电容器。 电容器可以是例如形成在衬底上或形成在衬底上的电介质层上的平面电容器。

公开(公告)号：US08552485B2

公开(公告)日：2013-10-08

申请号：US13161076

申请日：2011-06-15

申请人： Chun Hua Chang ,  Sung-Hui Huang ,  Der-Chyang Yeh

发明人： Chun Hua Chang ,  Sung-Hui Huang ,  Der-Chyang Yeh

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/40 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A first etch stop layer is disposed over the TSV structure. A first dielectric layer is disposed in contact with the first etch stop layer. A first conductive structure is disposed through the first etch stop layer and the first dielectric layer. The first conductive structure is electrically coupled with the TSV structure. The TSV structure is substantially wider than the first conductive structure. A second etch stop layer is disposed in contact with the first dielectric layer. A metal-insulator-metal (MIM) capacitor structure is disposed in contact with the second etch stop layer.

摘要翻译： 半导体结构包括设置在基板中的贯通基板通孔（TSV）结构。 第一蚀刻停止层设置在TSV结构上。 第一介电层设置成与第一蚀刻停止层接触。 通过第一蚀刻停止层和第一介电层设置第一导电结构。 第一导电结构与TSV结构电耦合。 TSV结构基本上比第一导电结构宽。 第二蚀刻停止层设置成与第一介电层接触。 金属 - 绝缘体 - 金属（MIM）电容器结构设置成与第二蚀刻停止层接触。

公开(公告)号：US08487410B2

公开(公告)日：2013-07-16

申请号：US13085668

申请日：2011-04-13

申请人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Ebin Liao ,  Chia-Lin Yu ,  Hsiang-Yi Wang ,  Chun Hua Chang ,  Li-Hsien Huang ,  Darryl Kuo ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Ebin Liao ,  Chia-Lin Yu ,  Hsiang-Yi Wang ,  Chun Hua Chang ,  Li-Hsien Huang ,  Darryl Kuo ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/481 ,  H01L23/49827 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.