公开(公告)号：US08487410B2

公开(公告)日：2013-07-16

申请号：US13085668

申请日：2011-04-13

申请人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Ebin Liao ,  Chia-Lin Yu ,  Hsiang-Yi Wang ,  Chun Hua Chang ,  Li-Hsien Huang ,  Darryl Kuo ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Ebin Liao ,  Chia-Lin Yu ,  Hsiang-Yi Wang ,  Chun Hua Chang ,  Li-Hsien Huang ,  Darryl Kuo ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/481 ,  H01L23/49827 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

公开(公告)号：US08525343B2

公开(公告)日：2013-09-03

申请号：US12892409

申请日：2010-09-28

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ebin Liao ,  Tsang-Jiuh Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ebin Liao ,  Tsang-Jiuh Wu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76831 ,  H01L21/486 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00

摘要： A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

摘要翻译： 具有通硅通孔（TSV）的器件及其形成方法包括在硅衬底中形成开口，在开口的侧壁和底部形成第一绝缘层，形成第二绝缘体 层在开口的侧壁和底部。 第一绝缘层和硅衬底之间的第一界面具有峰 - 谷高度小于5nm的界面粗糙度。 第二绝缘层与导电层之间的第二界面具有峰 - 谷高度小于5nm的界面粗糙度。

公开(公告)号：US08803322B2

公开(公告)日：2014-08-12

申请号：US13272506

申请日：2011-10-13

申请人： Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Yi-Hsiu Chen ,  Ebin Liao ,  Yuan-Hung Liu ,  Wen-Chih Chiou

发明人： Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Yi-Hsiu Chen ,  Ebin Liao ,  Yuan-Hung Liu ,  Wen-Chih Chiou

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05546 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill.

摘要翻译： 形成通过（TSV）通孔的结构的实施例能够降低由于层间电介质层（ILD）层的过度抛光而损坏栅极结构的风险。 在一端附近具有较宽开口的TSV结构还可实现更好的间隙填充。

公开(公告)号：US08674513B2

公开(公告)日：2014-03-18

申请号：US12779734

申请日：2010-05-13

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Tsang-Jiuh Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Tsang-Jiuh Wu

IPC分类号： H01L23/522

CPC分类号： H01L21/76895 ,  H01L21/563 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5283 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00

摘要： A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.

摘要翻译： 提供了一种与集成电路一起使用的装置。 该器件包括具有通过其形成的贯通基板通孔的基板。 电介质层形成在衬底的至少一侧上，并且在电介质层内形成金属化层。 最靠近贯穿衬底通孔的第一金属化层大于一个或多个上覆的金属化层。 在一个实施例中，顶部金属化层大于一个或多个下面的金属化层。 集成电路管芯可以在衬底的一侧或两侧附着到衬底，并且衬底的任一侧可以附接到另一个衬底，例如印刷电路板，高密度互连，封装衬底，有机 基板，层叠基板等。

公开(公告)号：US08847388B2

公开(公告)日：2014-09-30

申请号：US13267200

申请日：2011-10-06

申请人： Chen-Hua Yu ,  Hung-Pin Chang ,  An-Jhih Su ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Shin-Puu Jeng

发明人： Chen-Hua Yu ,  Hung-Pin Chang ,  An-Jhih Su ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/29

CPC分类号： H01L23/293 ,  H01L23/3192 ,  H01L24/01 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof.

摘要翻译： 半导体器件包括形成在钝化后互连（PPI）线上并由保护结构包围的凸块结构。 保护结构包括聚合物层和至少一个电介质层。 电介质层可以形成在聚合物层的顶表面上，该聚合物层的下面，插入凸起结构和聚合物层之间，插入在PPI线和聚合物层之间，覆盖聚合物层的外侧壁，或 其组合。

公开(公告)号：US08531035B2

公开(公告)日：2013-09-10

申请号：US13222639

申请日：2011-08-31

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76847 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

摘要： A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device.

摘要翻译： 提供了一种用于通过衬底通孔形成的系统和方法。 一个实施例包括在衬底中形成开口并且用第一阻挡层衬套开口。 开口填充有导电材料，并且形成与导电材料接触的第二阻挡层。 与第二阻挡层相比，第一阻挡层由不同的材料和不同的形成方法形成，使得材料和方法可被调整以使其在器件内的有效性最大化。

公开(公告)号：US20130001783A1

公开(公告)日：2013-01-03

申请号：US13222639

申请日：2011-08-31

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L21/76847 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

摘要： A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device.

公开(公告)号：US20120074562A1

公开(公告)日：2012-03-29

申请号：US12890094

申请日：2010-09-24

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu

IPC分类号： H01L23/485 ,  H01L21/762

CPC分类号： H01L25/0657 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06572

摘要： A device includes an interposer free from active devices therein. The interposer includes a substrate; a through-substrate via (TSV) penetrating through the substrate; and a low-k dielectric layer over the substrate.

摘要翻译： 一种器件包括其中没有有源器件的插入器。 插入件包括基板; 贯穿基板的贯穿基板通孔（TSV）; 以及在该衬底上的低k电介质层。

公开(公告)号：US20110278732A1

公开(公告)日：2011-11-17

申请号：US12779734

申请日：2010-05-13

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Tsang-Jiuh Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Tsang-Jiuh Wu

IPC分类号： H01L23/522 ,  H01L21/50

CPC分类号： H01L21/76895 ,  H01L21/563 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5283 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00

摘要： A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.

摘要翻译： 提供了一种与集成电路一起使用的装置。 该器件包括具有通过其形成的贯通基板通孔的基板。 电介质层形成在衬底的至少一侧上，并且在电介质层内形成金属化层。 最靠近贯穿衬底通孔的第一金属化层大于一个或多个上覆的金属化层。 在一个实施例中，顶部金属化层大于一个或多个下面的金属化层。 集成电路管芯可以在衬底的一侧或两侧附着到衬底，并且衬底的任一侧可以附接到另一衬底，例如印刷电路板，高密度互连，封装衬底，有机 基板，层叠基板等。

公开(公告)号：US08377796B2

公开(公告)日：2013-02-19

申请号：US12539374

申请日：2009-08-11

申请人： Chia-Lin Yu ,  Chen-Hua Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou

发明人： Chia-Lin Yu ,  Chen-Hua Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou

IPC分类号： H01L21/768

CPC分类号： H01L21/02365 ,  H01L21/02104 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02645 ,  H01L29/12

摘要： A method of forming a circuit structure includes providing a substrate; forming recesses in the substrate; forming a mask layer over the substrate, wherein the mask layer covers non-recessed portions of the substrate, with the recesses exposed through openings in the mask layer; forming a buffer/nucleation layer on exposed portions of the substrate in the recesses; and growing a group-III group-V (III-V) compound semiconductor material from the recesses until portions of the III-V compound semiconductor material grown from the recesses join each other to form a continuous III-V compound semiconductor layer.

摘要翻译： 形成电路结构的方法包括提供基板; 在基板上形成凹部; 在所述基板上形成掩模层，其中所述掩模层覆盖所述基板的非凹部，所述凹部通过所述掩模层中的开口暴露; 在所述凹部中的所述基板的暴露部分上形成缓冲/成核层; 以及从所述凹部生长第III族V族化合物半导体材料，直到从所述凹部生长的所述III-V族化合物半导体材料的部分相互连接形成连续的III-V族化合物半导体层。