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公开(公告)号：US08878338B2
公开(公告)日：2014-11-04
申请号：US13485340
申请日：2012-05-31
申请人： Chun Hua Chang , Der-Chyang Yeh , Kuang-Wei Cheng , Yuan-Hung Liu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
发明人： Chun Hua Chang , Der-Chyang Yeh , Kuang-Wei Cheng , Yuan-Hung Liu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
CPC分类号： H01L28/40 , H01L21/02 , H01L21/768 , H01L23/147 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L23/5223 , H01L23/53295 , H01L28/60 , H01L29/02 , H01L2924/0002 , H01L2924/00
摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.
摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在插入器中形成通孔，并且在下层金属化层和较高级金属化层之间形成电容器。 电容器可以是例如具有双电容器电介质层的平面电容器。
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公开(公告)号：US08765549B2
公开(公告)日：2014-07-01
申请号：US13458476
申请日：2012-04-27
申请人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
发明人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
IPC分类号： H01L21/8242
CPC分类号： H01L23/642 , H01L23/49822 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在一个实施例中，在通孔和下层金属化层之间形成电容器。 电容器可以是例如形成在衬底上或形成在衬底上的电介质层上的平面电容器。
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公开(公告)号：US20130285200A1
公开(公告)日：2013-10-31
申请号：US13458476
申请日：2012-04-27
申请人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
发明人： Chun Hua Chang , Shin-Puu Jeng , Der-Chyang Yeh , Shang-Yun Hou , Wen-Chih Chiou
CPC分类号： H01L23/642 , H01L23/49822 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
摘要翻译： 公开了用于衬底的电容器设计，例如插入件及其制造方法。 在一个实施例中，在通孔和下层金属化层之间形成电容器。 电容器可以是例如形成在衬底上或形成在衬底上的电介质层上的平面电容器。
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公开(公告)号：US20140042612A1
公开(公告)日：2014-02-13
申请号：US13569017
申请日：2012-08-07
CPC分类号： H01L23/5226 , H01L21/76807 , H01L23/147 , H01L23/49827 , H01L23/5223 , H01L23/5227 , H01L2924/0002 , H05K1/0215 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure.
摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在第一金属化层中在工件上形成第一导电结构，第一导电结构包括具有第一宽度的第一部分和具有第二宽度的第二部分。 第二宽度与第一宽度不同。 该方法包括在靠近第一金属化层的第二金属化层中形成第二导电结构，以及将第二导电结构的一部分耦合到第一导电结构的第一部分。
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公开(公告)号：US08937389B2
公开(公告)日：2015-01-20
申请号：US13569017
申请日：2012-08-07
IPC分类号： H01L23/48 , H01L21/4763 , H01L23/522 , H01L21/768 , H05K1/02
CPC分类号： H01L23/5226 , H01L21/76807 , H01L23/147 , H01L23/49827 , H01L23/5223 , H01L23/5227 , H01L2924/0002 , H05K1/0215 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure.
摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在第一金属化层中在工件上形成第一导电结构，第一导电结构包括具有第一宽度的第一部分和具有第二宽度的第二部分。 第二宽度与第一宽度不同。 该方法包括在靠近第一金属化层的第二金属化层中形成第二导电结构，以及将第二导电结构的一部分耦合到第一导电结构的第一部分。
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公开(公告)号：US08810006B2
公开(公告)日：2014-08-19
申请号：US13572240
申请日：2012-08-10
申请人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Der-Chyang Yeh
发明人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Der-Chyang Yeh
IPC分类号： H01L23/544 , H01L29/40
CPC分类号： H01L23/5381 , H01L21/486 , H01L21/563 , H01L23/147 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/0345 , H01L2224/0348 , H01L2224/0361 , H01L2224/03616 , H01L2224/0362 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14515 , H01L2224/16237 , H01L2224/2919 , H01L2224/29191 , H01L2224/32225 , H01L2224/73204 , H01L2224/81424 , H01L2224/81447 , H01L2224/81815 , H01L2224/81895 , H01L2224/83104 , H01L2224/83855 , H01L2224/92125 , H01L2224/97 , H01L2924/12042 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2924/014 , H01L2924/0665 , H01L2224/1144 , H01L2924/00
摘要： A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region.
摘要翻译： 提供了一种用于提供插入器的系统和方法。 一个实施例包括在第一区域和第二区域之间的划线区域上形成中介层晶片上的第一区域和第二区域。 然后，第一区域和第二区域通过位于划线区域上方的电路彼此连接。 在另一个实施例中，第一区域和第二区域可以彼此分离，然后在第一区域连接到第二区域之前封装在一起。
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公开(公告)号：US20140042643A1
公开(公告)日：2014-02-13
申请号：US13572240
申请日：2012-08-10
申请人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Der-Chyang Yeh
发明人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Der-Chyang Yeh
IPC分类号： H01L23/538 , H01L21/50
CPC分类号： H01L23/5381 , H01L21/486 , H01L21/563 , H01L23/147 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/0345 , H01L2224/0348 , H01L2224/0361 , H01L2224/03616 , H01L2224/0362 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14515 , H01L2224/16237 , H01L2224/2919 , H01L2224/29191 , H01L2224/32225 , H01L2224/73204 , H01L2224/81424 , H01L2224/81447 , H01L2224/81815 , H01L2224/81895 , H01L2224/83104 , H01L2224/83855 , H01L2224/92125 , H01L2224/97 , H01L2924/12042 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2924/014 , H01L2924/0665 , H01L2224/1144 , H01L2924/00
摘要： A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region.
摘要翻译： 提供了一种用于提供插入器的系统和方法。 一个实施例包括在第一区域和第二区域之间的划线区域上形成中介层晶片上的第一区域和第二区域。 然后，第一区域和第二区域通过位于划线区域上方的电路彼此连接。 在另一个实施例中，第一区域和第二区域可以彼此分离，然后在第一区域连接到第二区域之前封装在一起。
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公开(公告)号：US08105875B1
公开(公告)日：2012-01-31
申请号：US12904835
申请日：2010-10-14
申请人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号： H01L21/50
CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。
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公开(公告)号：US08759150B2
公开(公告)日：2014-06-24
申请号：US13488188
申请日：2012-06-04
申请人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号： H01L21/50
CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。
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公开(公告)号：US08693163B2
公开(公告)日：2014-04-08
申请号：US12873931
申请日：2010-09-01
申请人： An-Jhih Su , Chi-Chun Hsieh , Tzu-Yu Wang , Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
发明人： An-Jhih Su , Chi-Chun Hsieh , Tzu-Yu Wang , Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng
IPC分类号： H01L29/92 , H01L21/768
CPC分类号： H01L28/40 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/14 , H01L28/92 , H01L2224/0401 , H01L2224/05008 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14181 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.
摘要翻译： 一种装置包括具有与前表面相对的前表面和后表面的基底。 电容器形成在衬底中，并包括第一电容器板; 围绕所述第一电容器板的第一绝缘层; 以及环绕所述第一绝缘层的第二电容器板。 第一电容器板，第一绝缘层和第二电容器板中的每一个从基板的前表面延伸到后表面。
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