公开(公告)号：US20130170537A1

公开(公告)日：2013-07-04

申请号：US13407546

申请日：2012-02-28

Applicant: Chun Seok JEONG ,  Jae Jin LEE ,  Chang Sik YOO ,  Jang Woo LEE ,  Seok Joon KANG

Inventor： Chun Seok JEONG ,  Jae Jin LEE ,  Chang Sik YOO ,  Jang Woo LEE ,  Seok Joon KANG

IPC: H03H7/40

CPC classification number: H04L25/03038

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract translation: 数据均衡电路包括均衡器，其被配置为根据控制码的值控制数据的增益并输出控制器增益; 以及检测单元，被配置为将数据的n个周期分成N个周期，在改变控制码的值的同时，计算n / N个周期的数据转换频率，计算数据的1 / N个周期的数据转换频率的色散值， n / N周期的数据转换频率，最后输出对应于最大色散值的控制码的值，其中n等于或大于2，并且被设置为使得各个n / N周期的边界 数据在1 UI数据中具有不同的位置。

公开(公告)号：US20130170536A1

公开(公告)日：2013-07-04

申请号：US13407478

申请日：2012-02-28

Applicant: Chun Seok JEONG ,  Jae Jin LEE ,  Chang Sik YOO ,  Jang Woo LEE ,  Seok Joon KANG

Inventor： Chun Seok JEONG ,  Jae Jin LEE ,  Chang Sik YOO ,  Jang Woo LEE ,  Seok Joon KANG

IPC: H03H7/40

CPC classification number: H04L25/03878 ,  H04L25/03012

Abstract: A data equalizing circuit includes an equalizer configured to output data according to a control code; and a detection unit configured to divide the data into N number of calculation periods, count data transition frequencies for the N calculation periods, calculate dispersion values of the data transition frequencies for the N calculation periods, and output the control code corresponding to a largest dispersion value, in response to a counting interruption signal and a counting completion signal, wherein n is equal to or greater than 2, N is greater than n, and the data is divided to n number of unit intervals (UI), andwherein a phase shift of each of the calculation periods with respect to its corresponding UI is different from a phase shift of any of the other calculation periods with respect to its corresponding UI.

Abstract translation: 数据均衡电路包括：均衡器，被配置为根据控制码输出数据; 以及检测单元，被配置为将数据划分为N个计算周期，用于N个计算周期的计数数据转换频率，计算N个计算周期的数据转换频率的色散值，并输出与最大色散对应的控制码 响应于计数中断信号和计数完成信号，其中n等于或大于2，N大于n，并且数据被划分为n个单位间隔（UI），并且其中相位 每个计算周期相对于其对应的UI的移位不同于任何其他计算周期相对于其对应的UI的相移。

公开(公告)号：US20120182042A1

公开(公告)日：2012-07-19

申请号：US13162676

申请日：2011-06-17

Applicant: Chun Seok JEONG ,  Jae Jin LEE

Inventor： Chun Seok JEONG ,  Jae Jin LEE

IPC: H03K19/003

CPC classification number: G11C7/20 ,  G11C29/883 ,  G11C2029/4402 ,  H01L2224/16

Abstract: A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code.

Abstract translation: 具有第一和第二芯片的半导体装置包括设置在第一芯片中的第一操作单元，并且被配置为根据第一修复信号对初始码执行预定的算术运算，并生成第一操作码; 以及第二操作单元，设置在所述第二芯片中，并且被配置为根据第二修复信号对所述第一操作码执行所述预定算术运算，并生成第二操作码。

公开(公告)号：US20130001548A1

公开(公告)日：2013-01-03

申请号：US13339018

申请日：2011-12-28

Applicant: Chun Seok JEONG ,  Jae Jin LEE

Inventor： Chun Seok JEONG ,  Jae Jin LEE

IPC: H01L25/07 ,  H01L23/48

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06596

Abstract: A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

Abstract translation: 半导体装置包括被形成为与另一个芯片电连接的TSV以及被配置为检查TSV的电容分量以产生TSV异常信号的TSV测试单元。

公开(公告)号：US20100329040A1

公开(公告)日：2010-12-30

申请号：US12649066

申请日：2009-12-29

Applicant: Chun Seok JEONG ,  Kee Teok PARK ,  Chang Sik YOO ,  Jang Woo LEE ,  Hong Jung KIM

Inventor： Chun Seok JEONG ,  Kee Teok PARK ,  Chang Sik YOO ,  Jang Woo LEE ,  Hong Jung KIM

IPC: G11C7/10 ,  G11C7/00 ,  G11C8/18

CPC classification number: G11C7/22 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222

Abstract: A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.

Abstract translation: 半导体存储装置的数据对准电路包括：数据选通时钟相位控制块，被配置为响应于选通延迟码来控制数据选通时钟信号的相位，并产生延迟的选通时钟信号; 多个数据相位控制块，被配置为响应于数据延迟码来控制输入数据的相位并产生延迟的数据; 多个数据对准块被配置为响应延迟的选通时钟信号来锁存延迟的数据，并产生锁存的数据和对准的数据; 以及延迟码生成块，被配置为执行确定所述锁存数据的相位的操作，并生成所述选通延迟码和所述数据延迟码。

公开(公告)号：US20130135942A1

公开(公告)日：2013-05-30

申请号：US13341005

申请日：2011-12-30

Applicant: Chun Seok JEONG

Inventor： Chun Seok JEONG

IPC: G11C7/10

CPC classification number: G11C7/1039

Abstract: A pipe latch control circuit and a semiconductor integrated circuit using the same are provided. The pipe latch control circuit includes a read command control unit that receives a first signal and generates a read signal in response to a control signal. In the pipe latch control circuit, the read command control unit selects, in response to the control signal, the first signal or selects a second signal obtained by delaying the first signal according to an internal clock, and generates the selected first or second signal as the read signal.

Abstract translation: 提供了管闩锁控制电路和使用其的半导体集成电路。 管闩锁控制电路包括读命令控制单元，其接收第一信号并响应于控制信号产生读信号。 在管锁存控制电路中，读指令控制单元响应于控制信号选择第一信号，或者选择通过根据内部时钟延迟第一信号而获得的第二信号，并将所选择的第一或第二信号作为 读信号。

公开(公告)号：US20120194244A1

公开(公告)日：2012-08-02

申请号：US13166051

申请日：2011-06-22

Applicant: Yong Hoon KIM ,  Chun Seok JEONG

Inventor： Yong Hoon KIM ,  Chun Seok JEONG

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: A semiconductor memory apparatus may comprise a duty cycle correction circuit configured to perform a duty correction operation with respect to an input clock signal when a delay locked signal is activated, and perform the duty correction operation with respect to the input signal when a precharge signal is activated, to generate a corrected clock signal.

Abstract translation: 半导体存储装置可以包括占空比校正电路，其被配置为当延迟锁定信号被激活时对输入时钟信号执行占空比校正操作，并且当预充电信号为...时，对输入信号执行占空比校正操作 激活，以产生校正的时钟信号。

公开(公告)号：US20130002276A1

公开(公告)日：2013-01-03

申请号：US13340841

申请日：2011-12-30

Applicant: Chun Seok JEONG

Inventor： Chun Seok JEONG

IPC: G01R31/3187 ,  H01L23/58

CPC classification number: G01R31/31717 ,  G11C29/025 ,  G11C2029/5002 ,  H01L22/34 ,  H01L23/481 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a through via and a comparison unit. The through via is electrically connected with another chip. The comparison unit includes a reference capacitor, and compares a capacitance value of the through via and a capacitance value of the reference capacitor in response to a test start signal and a reset signal and generates a comparison result.

Abstract translation: 半导体装置包括通孔和比较单元。 通孔与另一个芯片电连接。 比较单元包括参考电容器，并且响应于测试开始信号和复位信号，比较通孔的电容值和参考电容器的电容值，并产生比较结果。