公开(公告)号：US20050035345A1

公开(公告)日：2005-02-17

申请号：US10832020

申请日：2004-04-26

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/06

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

摘要翻译： 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

公开(公告)号：US20060177997A1

公开(公告)日：2006-08-10

申请号：US11377105

申请日：2006-03-16

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

IPC分类号： H01L21/20

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

摘要翻译： 提供一种制造集成电路的方法。 第一栅介质部分形成在第一晶体管区域中的衬底上。 第一栅介质部分包括第一高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 在第二晶体管区域中的衬底上形成第二栅介质部分。 第二栅介质部分包括第一高电容率介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度不同于第一等效氧化硅厚度。

公开(公告)号：US07354830B2

公开(公告)日：2008-04-08

申请号：US11377105

申请日：2006-03-16

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Yee-Chia Yeo

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Yee-Chia Yeo

IPC分类号： H01L21/8234

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

摘要翻译： 提供一种制造集成电路的方法。 第一栅介质部分形成在第一晶体管区域中的衬底上。 第一栅介质部分包括第一高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 在第二晶体管区域中的衬底上形成第二栅介质部分。 第二栅介质部分包括第一高电容率介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度不同于第一等效氧化硅厚度。

公开(公告)号：US07045847B2

公开(公告)日：2006-05-16

申请号：US10832020

申请日：2004-04-26

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Ye-Chia Yeng

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Ye-Chia Yeng

IPC分类号： H01L27/108

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

摘要翻译： 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

公开(公告)号：US20050224897A1

公开(公告)日：2005-10-13

申请号：US10809974

申请日：2004-03-26

申请人： Shang-Chih Chen ,  Chih-Hao Wang ,  Yee-Chia Yeo ,  Feng-Der Chin ,  Chuan-Yi Lin

发明人： Shang-Chih Chen ,  Chih-Hao Wang ,  Yee-Chia Yeo ,  Feng-Der Chin ,  Chuan-Yi Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78 ,  H01L39/22

CPC分类号： H01L29/517 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/78

摘要： A high-K gate dielectric stack for a MOSFET gate structure to reduce Voltage threshold (Vth) shifts and method for forming the same, the method including providing a high-K gate dielectric layer over a semiconductor substrate; forming a buffer dielectric layer on the high-K gate dielectric including a dopant selected from the group consisting of a metal, a semiconductor, and nitrogen; forming a gate electrode layer on the buffer dielectric layer; and, lithographically patterning the gate electrode layer and etching to form a gate structure.

摘要翻译： 用于降低电压阈值（V SUB）的MOSFET栅极结构的高K栅极电介质叠层及其形成方法，所述方法包括在半导体衬底上提供高K栅介质层 ; 在包括选自金属，半导体和氮的掺杂剂的高K栅极电介质上形成缓冲介电层; 在所述缓冲电介质层上形成栅电极层; 并且平版印刷图案化栅极电极层和蚀刻以形成栅极结构。

公开(公告)号：US20120083076A1

公开(公告)日：2012-04-05

申请号：US13324592

申请日：2011-12-13

申请人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

发明人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。 栅极电介质突出超过栅电极。 在栅极的任一侧形成具有浅延伸的深源极和漏极。 深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。 延伸部位于与栅极电介质接触的栅极下方。 选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。 描述制造MOSFET的方法。

公开(公告)号：US08759185B2

公开(公告)日：2014-06-24

申请号：US13324592

申请日：2011-12-13

申请人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

发明人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。 栅极电介质突出超过栅电极。 在栅极的任一侧形成具有浅延伸的深源极和漏极。 深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。 延伸部位于与栅极电介质接触的栅极下方。 选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。 描述制造MOSFET的方法。

公开(公告)号：US08097924B2

公开(公告)日：2012-01-17

申请号：US10872095

申请日：2004-06-18

申请人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

发明人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/1054 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。 栅极电介质突出超过栅电极。 在栅极的任一侧形成具有浅延伸的深源极和漏极。 深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。 延伸部位于与栅极电介质接触的栅极下方。 选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。 描述制造MOSFET的方法。

公开(公告)号：US20050093084A1

公开(公告)日：2005-05-05

申请号：US10872095

申请日：2004-06-18

申请人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

发明人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/1054 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。 栅极电介质突出超过栅电极。 在栅极的任一侧形成具有浅延伸的深源极和漏极。 深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。 延伸部位于与栅极电介质接触的栅极下方。 选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。 描述制造MOSFET的方法。

公开(公告)号：US07229893B2

公开(公告)日：2007-06-12

申请号：US11021269

申请日：2004-12-23

申请人： Chih-Hao Wang ,  Ching-Wei Tsai ,  Shang-Chih Chen

发明人： Chih-Hao Wang ,  Ching-Wei Tsai ,  Shang-Chih Chen

IPC分类号： H01L21/76

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10894

摘要： A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.

摘要翻译： 描述了一种高栅极介电MOS晶体管的工艺和装置。 提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。 侧壁材料沉积在图案化的栅极电极上，并且在图案化的栅电极和在电介质的底部下方延伸的电介质上形成电介质。 在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。 在替代实施例中，沟道材料是反掺杂的。