公开(公告)号：US08610524B2

公开(公告)日：2013-12-17

申请号：US13456689

申请日：2012-04-26

Applicant: Chun-Ching Yen ,  Yu-Jen Huang

Inventor： Chun-Ching Yen ,  Yu-Jen Huang

IPC: H01F27/06 ,  H01F27/29 ,  H01F27/30

CPC classification number: H01F27/027 ,  H01F27/266 ,  H01F27/306 ,  H01F2027/297

Abstract: A transformer includes a base, a magnetic core unit and a winding assembly. The base includes a base body and a pin disposed on the base body. The magnetic core unit is disposed in the base body, and the winding assembly is disposed in the magnetic core unit. A winding of the winding assembly is connected to the pin.

Abstract translation: 变压器包括基座，磁芯单元和绕组组件。 基座包括基体和设置在基体上的销。 磁芯单元设置在基体中，并且绕组组件设置在磁芯单元中。 绕组组件的绕组连接到销。

公开(公告)号：US20130015933A1

公开(公告)日：2013-01-17

申请号：US13456689

申请日：2012-04-26

Applicant: Chun-Ching YEN ,  Yu-Jen Huang

Inventor： Chun-Ching YEN ,  Yu-Jen Huang

IPC: H01F27/29

CPC classification number: H01F27/027 ,  H01F27/266 ,  H01F27/306 ,  H01F2027/297

Abstract: A transformer includes a base, a magnetic core unit and a winding assembly. The base includes a base body and a pin disposed on the base body. The magnetic core unit is disposed in the base body, and the winding assembly is disposed in the magnetic core unit. A winding of the winding assembly is connected to the pin.

Abstract translation: 变压器包括基座，磁芯单元和绕组组件。 基座包括基体和设置在基体上的销。 磁芯单元设置在基体中，并且绕组组件设置在磁芯单元中。 绕组组件的绕组连接到销。

公开(公告)号：US20120306788A1

公开(公告)日：2012-12-06

申请号：US13483034

申请日：2012-05-29

Applicant: Kai-Yi Chen ,  Yi-Chen Sung ,  Yu-Jen Huang ,  Chia-Chen Wang ,  Yen-Lin Lin ,  Hsiu-Hang Lin ,  Hui Lin ,  Chih-Yen Lan ,  Pei-Ching Hu ,  Yung-Yu Huang

Inventor： Kai-Yi Chen ,  Yi-Chen Sung ,  Yu-Jen Huang ,  Chia-Chen Wang ,  Yen-Lin Lin ,  Hsiu-Hang Lin ,  Hui Lin ,  Chih-Yen Lan ,  Pei-Ching Hu ,  Yung-Yu Huang

IPC: G06F3/041

CPC classification number: G06F3/0482 ,  G06F3/04883 ,  G06F3/04886

Abstract: An electronic apparatus with a touch input system is provided. When a complete touch signal is detected, a sliding angle and a sliding track of the complete touch signal are calculated. A menu operation interface with arc-shaped arrangement is displayed in a touch display screen when the sliding angle of the complete touch signal exceeds a predetermined angle. And when an incomplete touch signal is detected, a sliding angle and a sliding track of the incomplete touching signal are calculated for displaying a part of the menu operation interface with arc-shaped arrangement in the touch display screen.

Abstract translation: 提供具有触摸输入系统的电子设备。 当检测到完整的触摸信号时，计算完整触摸信号的滑动角度和滑动轨迹。 当完整的触摸信号的滑动角超过预定角度时，在触摸显示屏幕中显示具有弧形排列的菜单操作界面。 并且当检测到不完整的触摸信号时，计算不完全触摸信号的滑动角度和滑动轨迹，以在触摸显示屏幕中显示具有弧形排列的菜单操作界面的一部分。

公开(公告)号：US08379133B2

公开(公告)日：2013-02-19

申请号：US12963846

申请日：2010-12-09

Applicant: Chia-Ching Tso ,  Yu-Jen Huang ,  Chih-Hao Lin

Inventor： Chia-Ching Tso ,  Yu-Jen Huang ,  Chih-Hao Lin

IPC: H04N5/225

CPC classification number: H04N5/2253 ,  H04N5/2257 ,  Y10T29/53174

Abstract: A holder is disclosed, wherein the holder is situated on a circuit board and is used for connecting with an electronic component. The holder comprises an upper surface, a lower surface, and an opening. The upper surface comprises a recess used for laying a flat component, wherein the recess comprises at least one rough area; the lower surface comprises a protruding edge, wherein the protruding edge is connected with the circuit board with glue, and the protruding side and the circuit board delimit a space; and the opening penetrates the upper surface and the lower surface, whereby the gas generated from heating the glue will accumulate in the enclosed space, and the gas will then escape through the opening and out through at least one of the rough areas.

Abstract translation: 公开了一种保持器，其中保持器位于电路板上并且用于与电子部件连接。 保持器包括上表面，下表面和开口。 上表面包括用于铺设平坦部件的凹槽，其中凹部包括至少一个粗糙区域; 所述下表面包括突出边缘，其中所述突出边缘与所述电路板连接，并且所述突出侧和所述电路板限定空间; 并且开口穿透上表面和下表面，由此由加热胶水产生的气体将积聚在封闭空间中，然后气体将通过开口逸出并穿过至少一个粗糙区域。

公开(公告)号：US20100245242A1

公开(公告)日：2010-09-30

申请号：US12751220

申请日：2010-03-31

Applicant: Yi-Hsi WU ,  Huang-Ming Chang ,  Yu-Jen Huang ,  Hong-Tien Wang

Inventor： Yi-Hsi WU ,  Huang-Ming Chang ,  Yu-Jen Huang ,  Hong-Tien Wang

IPC: G09G5/08

CPC classification number: G06F3/0488

Abstract: An electronic device and a method of operating a screen are disclosed; the touch screen has a display area and a non-display area, and the method includes steps as follows. First, a first sensing signal is generated when a designator controls a pointer on the non-display area. Then, a second sensing signal is generated when the pointer is moved from the non-display area to the display area. Then, a third sensing signal is generated when the pointer is moved on the display area. Last, a user interface is opened in the display area when a processing module receives the first, second and third sensing signals sequentially.

Abstract translation: 公开了一种电子设备和操作屏幕的方法; 触摸屏具有显示区域和非显示区域，并且该方法包括以下步骤。 首先，当指示器控制非显示区域上的指针时，产生第一感测信号。 然后，当指针从非显示区域移动到显示区域时，产生第二感测信号。 然后，当指示器在显示区域上移动时，产生第三感测信号。 最后，当处理模块顺序地接收第一，第二和第三感测信号时，在显示区域中打开用户界面。

公开(公告)号：US07596728B2

公开(公告)日：2009-09-29

申请号：US11870169

申请日：2007-10-10

Applicant: Tsu-Wei Tseng ,  Yu-Jen Huang ,  Chun-Hsien Wu ,  Jin-Fu Li ,  Chien-Yuan Pao

Inventor： Tsu-Wei Tseng ,  Yu-Jen Huang ,  Chun-Hsien Wu ,  Jin-Fu Li ,  Chien-Yuan Pao

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C29/44 ,  G11C8/16 ,  G11C29/4401 ,  G11C29/808

Abstract: A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.

Abstract translation: 提供了一种用于多端口存储器的内置自修复（BISR）电路及其方法。 电路包括测试和分析模块（TAM）和耦合到TAM的缺陷定位模块（DLM）。 TAM测试可修复的多端口内存以产生故障位置，并确定测试是否根据故障位置生成端口特定的故障候选。 如果生成了特定于端口的故障候选，则DLM根据故障位置生成缺陷位置，并向TAM提供缺陷位置，以便TAM根据缺陷位置确定如何修复可修复的多端口存储器。 如果在测试中没有生成端口特定的故障候选，则TAM根据故障位置确定如何修复可修复的多端口存储器。

公开(公告)号：US20120180000A1

公开(公告)日：2012-07-12

申请号：US13073974

申请日：2011-03-28

Applicant: Ming-Che Weng ,  Wei-Ling Hsu ,  Yu-Jen Huang ,  Pei-Fen Deng ,  Chun-Cheng Chen ,  Shi-Kuan Chen ,  Hong-Tien Wang

Inventor： Ming-Che Weng ,  Wei-Ling Hsu ,  Yu-Jen Huang ,  Pei-Fen Deng ,  Chun-Cheng Chen ,  Shi-Kuan Chen ,  Hong-Tien Wang

IPC: G06F3/048

CPC classification number: G06T19/00 ,  G06F3/04815 ,  G06T2200/24

Abstract: A method and a system for simulating a three-dimensional (3D) operating interface are provided. The method includes defining a partition line to partition a display frame of a screen into a first area and a second area, and defining a size of a unit grid to establish a first grid plane and a second grid plane in the first area and the second area respectively, the first grid plane and the second grid plane forming a simulated 3D grid space. The method also includes taking the unit grid as a unit to define an object size and an initial grid coordinate of an object. The initial grid coordinate is on one of the first and the second grid planes. The method further includes mapping out a simulated 3D space in the simulated 3D grid space for displaying the object according to the initial grid coordinate and the object size.

Abstract translation: 提供了一种用于模拟三维（3D）操作界面的方法和系统。 该方法包括定义分割线以将屏幕的显示帧划分为第一区域和第二区域，并且定义单位格栅的大小以在第一区域和第二区域中建立第一格子平面和第二格子平面 区域，第一格架平面和第二格子平面形成模拟3D网格空间。 该方法还包括以单位网格为单位来定义对象的对象大小和初始网格坐标。 初始网格坐标位于第一和第二网格平面中的一个上。 该方法还包括在模拟3D网格空间中映射模拟3D空间，以根据初始网格坐标和对象大小显示对象。

公开(公告)号：US08062487B2

公开(公告)日：2011-11-22

申请号：US11768192

申请日：2007-06-25

Applicant: Chi-Piao Cheng ,  Li-Chun Liang ,  Yu-Jen Huang ,  Been Chen ,  Sheng-Yih Ting

Inventor： Chi-Piao Cheng ,  Li-Chun Liang ,  Yu-Jen Huang ,  Been Chen ,  Sheng-Yih Ting

IPC: C25B9/00 ,  C25B11/00 ,  C25B13/00 ,  C23C14/00 ,  C23C16/00 ,  C23C16/50

CPC classification number: C23C14/50 ,  H01J37/32623 ,  H01J37/32642 ,  H01J37/32706

Abstract: A wafer supporting device of a sputter apparatus includes a pedestal positioned in a sputtering chamber and used to load a wafer for sputtering, a deposition ring having a recess positioned on a peripheral portion of the pedestal, and a cover ring positioned on the pedestal and the deposition ring. The cover ring has a gate corresponding to the recess.

Abstract translation: 溅射装置的晶片支撑装置包括位于溅射室中并用于装载用于溅射的晶片的基座，具有位于基座的周边部分上的凹部的沉积环和位于基座上的盖环， 沉积环。 盖环具有对应于凹部的门。

公开(公告)号：US07610535B2

公开(公告)日：2009-10-27

申请号：US11747922

申请日：2007-05-14

Applicant: Yu-Jen Huang ,  Chih-Hung Lin

Inventor： Yu-Jen Huang ,  Chih-Hung Lin

IPC: G01R31/309 ,  G01R31/40

CPC classification number: G06F17/5077 ,  G01R31/2815 ,  G01R31/318591 ,  G06F17/5081 ,  G06F2217/40

Abstract: Read the description file of a PCBA without determining and selecting connectors which might be relevant to boundary scan. The description file of the PCBA determines which pins of the connectors on the PCBA should correspond to the pins of a test I/O module. And use the wiring report generated by an auto test program generator to correspond the pins of the test I/O module to the pins of the connectors which are accessed by boundary scan. Thus the IC of the test I/O module would not have any unused pin between any two consecutive pins wired to the connectors of the PCBA.

Abstract translation: 阅读PCBA的描述文件，而无需确定和选择可能与边界扫描相关的连接器。 PCBA的描述文件确定PCBA上的连接器的哪些引脚应对应于测试I / O模块的引脚。 并使用自动测试程序生成器生成的接线报告将测试I / O模块的引脚对应到通过边界扫描访问的连接器的引脚。 因此，测试I / O模块的IC在连接到PCBA的连接器的任何两个连续引脚之间不会有任何未使用的引脚。

公开(公告)号：US20090097342A1

公开(公告)日：2009-04-16

申请号：US11870169

申请日：2007-10-10

Applicant: Tsu-Wei Tseng ,  Yu-Jen Huang ,  Chun-Hsien Wu ,  Jin-Fu Li ,  Chien-Yuan Pao

Inventor： Tsu-Wei Tseng ,  Yu-Jen Huang ,  Chun-Hsien Wu ,  Jin-Fu Li ,  Chien-Yuan Pao

IPC: G11C29/12

CPC classification number: G11C29/44 ,  G11C8/16 ,  G11C29/4401 ,  G11C29/808

Abstract: A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.

Abstract translation: 提供了一种用于多端口存储器的内置自修复（BISR）电路及其方法。 该电路包括测试和分析模块（TAM）和耦合到TAM的缺陷定位模块（DLM）。 TAM测试可修复的多端口存储器以产生故障位置，并根据故障位置确定测试是否生成端口特定故障候选。 如果生成了特定于端口的故障候选，则DLM根据故障位置生成缺陷位置，并向TAM提供缺陷位置，以便TAM根据缺陷位置确定如何修复可修复的多端口存储器。 如果在测试中没有生成端口特定的故障候选，则TAM根据故障位置确定如何修复可修复的多端口存储器。