公开(公告)号：US20130025830A1

公开(公告)日：2013-01-31

申请号：US13191612

申请日：2011-07-27

申请人： Chun-Hung LIN ,  Yen-Hsiang CHIU ,  Tung-Yang SHIEH ,  Chun-Yi LEE

发明人： Chun-Hung LIN ,  Yen-Hsiang CHIU ,  Tung-Yang SHIEH ,  Chun-Yi LEE

IPC分类号： F28D15/04

CPC分类号： F28D15/0275 ,  F28D2021/0029 ,  F28F1/32 ,  F28F2275/04 ,  F28F2275/122

摘要： A heat sink assembly includes a fin module, heat pipes, and a pair of side plates. The fin module is composed of a plurality of fins and has a flat side formed with a trough and two recesses. Each of the heat pipes has an evaporation section. The evaporation sections are parallelly accommodated in the trough and in contact with each other. The side plates are separately fixed in the recesses and protrude from the flat side. The evaporation sections are formed with a flat surface coplanar with the side plates. By this arrangement, the thermal contact area between the heat pipes and a heat source is increased to thereby improve the heat-dissipating efficiency of the heat sink assembly.

摘要翻译： 散热器组件包括翅片模块，热管和一对侧板。 翅片模块由多个翅片组成，并且具有形成有凹槽和两个凹部的平坦侧。 每个热管具有蒸发部。 蒸发部分平行地容纳在槽中并彼此接触。 侧板分别固定在凹部中并从平坦侧突出。 蒸发部分形成有与侧板共面的平坦表面。 通过这种布置，热管和热源之间的热接触面积增加，从而提高散热器组件的散热效率。

公开(公告)号：US20120318480A1

公开(公告)日：2012-12-20

申请号：US13160555

申请日：2011-06-15

申请人： Chun-Hung LIN ,  Tung-Yang SHIEH ,  Yen-Hsiang CHIU ,  Chun-Yi LEE

发明人： Chun-Hung LIN ,  Tung-Yang SHIEH ,  Yen-Hsiang CHIU ,  Chun-Yi LEE

IPC分类号： F28D15/04 ,  B21D53/02

CPC分类号： F28D15/0233 ,  F28D15/0275 ,  F28D2021/0028 ,  F28F1/32 ,  F28F2275/04 ,  F28F2275/122 ,  Y10T29/4935

摘要： The present invention relates to a heat sink having juxtaposed heat pipes and a method for manufacturing the same. The heat sink includes a base, a plurality of heat pipes and a pair of side strips. The base has a surface on which an open trough and an insertion trough on both sides of the open trough are provided. Each heat pipe has an evaporating section. The evaporating sections are juxtaposed in the open trough and adhered to each other. Each evaporating section has a planar surface. The side strips are fixed into the insertion troughs and protrude from the surface of the base. The planar surface of each evaporating section and the outer surface of each side strip are coplanar. By this structure, the thermal contact surface between the heat pipes and electronic heat-generating sources is increased, so that the heat-dissipating efficiency of the heat sink is improved.

摘要翻译： 本发明涉及具有并置热管的散热器及其制造方法。 散热器包括基座，多个热管和一对侧条。 底座具有一个表面，在该表面上设置开口槽和开口槽两侧的插槽。 每个热管都有一个蒸发部分。 蒸发部分在开槽中并列并相互粘合。 每个蒸发部分具有平坦的表面。 侧条固定在插入槽中并从基座的表面突出。 每个蒸发段的平面和每个侧条的外表面是共面的。 通过这种结构，热管和电子发热源之间的热接触表面增加，从而提高了散热器的散热效率。

公开(公告)号：US20130102138A1

公开(公告)日：2013-04-25

申请号：US13280770

申请日：2011-10-25

申请人： Ming-Hsi YEH ,  Tsung-Chieh TSAI ,  Chun-Yi LEE

发明人： Ming-Hsi YEH ,  Tsung-Chieh TSAI ,  Chun-Yi LEE

IPC分类号： H01L21/28

CPC分类号： H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092

摘要： A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature.

摘要翻译： 公开了一种制造半导体器件的方法。 在衬底上的层间电介质（ILD）中的两个有源栅极特征之间形成虚拟栅极特征。 隔离结构位于衬底中，虚拟栅极特征位于隔离结构之上。 源极/漏极（S / D）特征形成在用于形成晶体管器件的衬底中的有源栅极特征的边缘处。 所公开的方法提供了一种用于减小晶体管器件之间的寄生电容的改进方法。 在一个实施例中，通过将物质引入虚拟栅极特征来增加虚拟栅极特征的电阻来实现改进的形成方法。

公开(公告)号：US20120175602A1

公开(公告)日：2012-07-12

申请号：US13425284

申请日：2012-03-20

申请人： Jenn-Chang HWANG ,  Li-Shiuan TSAI ,  Chun-Yi LEE ,  Cheng-Lun TSAI

发明人： Jenn-Chang HWANG ,  Li-Shiuan TSAI ,  Chun-Yi LEE ,  Cheng-Lun TSAI

IPC分类号： H01L51/10 ,  H01L51/40

CPC分类号： H01L51/0055 ,  B82Y10/00 ,  H01L28/40 ,  H01L51/0046 ,  H01L51/0053 ,  H01L51/0093 ,  H01L51/052 ,  H01L51/0545 ,  H01L51/0562

摘要： An N-type organic thin film transistor, an ambipolar field-effect transistor, and methods of fabricating the same are disclosed. The N-type organic thin film transistor of the present invention comprises: a substrate; a gate electrode locating on the substrate; a gate-insulating layer covering the gate electrode, and the gate-insulating layer is made of silk protein; a buffering layer locating on the gate-insulating layer, and the buffering layer is made of pentacene; an N-type organic semiconductor layer locating on the buffering layer; and a source and a drain electrode, wherein the N-type organic semiconductor layer, the buffering layer, the source and the drain electrode are disposed over the gate dielectric layer.

摘要翻译： 公开了一种N型有机薄膜晶体管，双极场效应晶体管及其制造方法。 本发明的N型有机薄膜晶体管包括：基板; 位于基板上的栅电极; 覆盖栅电极的栅极绝缘层，栅绝缘层由丝蛋白制成; 位于栅极绝缘层上的缓冲层，缓冲层由并五苯制成; 位于缓冲层上的N型有机半导体层; 以及源极和漏极，其中所述N型有机半导体层，所述缓冲层，所述源极和漏极被设置在所述栅极介电层上。

公开(公告)号：US20090295419A1

公开(公告)日：2009-12-03

申请号：US12256042

申请日：2008-10-22

申请人： Kuen-Long CHANG ,  Chun-Hsiung HUNG ,  Chuan-Ying YU ,  Chun-Yi LEE

发明人： Kuen-Long CHANG ,  Chun-Hsiung HUNG ,  Chuan-Ying YU ,  Chun-Yi LEE

IPC分类号： G01R31/3187

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

摘要翻译： 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

公开(公告)号：US20130105204A1

公开(公告)日：2013-05-02

申请号：US13417869

申请日：2012-03-12

申请人： Jenn-Chang HWANG ,  Chao-Ying HSIEH ,  Chwung-Shan KOU ,  Chung-Hwa WANG ,  Li-Shiuan TSAI ,  Lung-Kai MAO ,  Shih-Jie JIAN ,  Jian-You LIN ,  Chun-Yi LEE

发明人： Jenn-Chang HWANG ,  Chao-Ying HSIEH ,  Chwung-Shan KOU ,  Chung-Hwa WANG ,  Li-Shiuan TSAI ,  Lung-Kai MAO ,  Shih-Jie JIAN ,  Jian-You LIN ,  Chun-Yi LEE

IPC分类号： H05K1/03 ,  H05K1/02 ,  H05K1/09 ,  H05K3/00

CPC分类号： H05K1/0346 ,  H05K1/0393 ,  H05K3/0041 ,  H05K3/4676 ,  H05K2203/178 ,  Y10T29/49124

摘要： A circuit board and a method for manufacturing the same are disclosed. The circuit board of the present invention comprises: a carrier board, wherein a first circuit layer is disposed on at least one surface of the carrier board, and the first circuit layer comprises plural conductive pads; a protein dielectric layer disposed on the surface of the carrier board and the first circuit layer, wherein the protein dielectric layer has plural openings to expose the conductive pads; and a second circuit layer disposed on a surface of the protein dielectric layer, wherein the second circuit layer comprises plural first conductive vias, and each first conductive via is correspondingly formed in the opening and electrically connects to the conductive pad.

摘要翻译： 公开了一种电路板及其制造方法。 本发明的电路板包括：承载板，其中第一电路层设置在载板的至少一个表面上，第一电路层包括多个导电焊盘; 设置在所述载体板和所述第一电路层的表面上的蛋白质电介质层，其中所述蛋白质介电层具有多个开口以暴露所述导电焊盘; 以及设置在所述蛋白质电介质层的表面上的第二电路层，其中所述第二电路层包括多个第一导电通孔，并且每个第一导电通孔相应地形成在所述开口中并且电连接到所述导电焊盘。

公开(公告)号：US20130052813A1

公开(公告)日：2013-02-28

申请号：US13221214

申请日：2011-08-30

申请人： Ming-Hsi YEH ,  Chun-Yi LEE ,  Chi-Ming YANG ,  Chin-Hsiang LIN

发明人： Ming-Hsi YEH ,  Chun-Yi LEE ,  Chi-Ming YANG ,  Chin-Hsiang LIN

IPC分类号： H01L21/425

CPC分类号： H01L21/823431 ,  H01L21/28255 ,  H01L21/28264 ,  H01L29/513 ,  H01L29/517

摘要： Provided is a method and structure for utilizing advance channel substrate materials in semiconductor manufacturing. Advanced channel substrate materials such as germanium and Group III-V channel substrate materials, are advantageously utilized. One or more capping films including at least a nitride layer are formed over the channel substrate prior to patterning, ion implantation and the subsequent stripping and wet cleaning operations. With the capping layers intact during these operations, attack of the channel substrate material is prevented and the protective films are easily removed subsequently. The films are dimensioned in conjunction with the ion implantation operation to enable the desired dopant profile and concentration to be formed in the channel substrate material.

摘要翻译： 提供了一种在半导体制造中利用前置沟道衬底材料的方法和结构。 可以有利地利用诸如锗和III-V族通道衬底材料的高级通道衬底材料。 在图案化，离子注入和随后的剥离和湿式清洗操作之前，在沟道基底上方形成至少包含至少氮化物层的一个或多个封盖膜。 在这些操作期间，封盖层完好无损，防止了通道衬底材料的侵蚀，随后保护膜很容易被去除。 这些膜的尺寸与离子注入操作相结合，使得能够在通道衬底材料中形成所需的掺杂剂分布和浓度。