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    MOSFET dielectric including a diffusion barrier
    1.
    发明申请
    MOSFET dielectric including a diffusion barrier 审中-公开
    MOSFET电介质包括扩散阻挡层

    公开(公告)号：US20070096226A1

    公开(公告)日：2007-05-03

    申请号：US11264069

    申请日：2005-10-31

    申请人： Chun-Li Liu ,  Tushar Merchant ,  Marius Orlowski ,  James Schaeffer ,  Matthew Stoker

    发明人： Chun-Li Liu ,  Tushar Merchant ,  Marius Orlowski ,  James Schaeffer ,  Matthew Stoker

    IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

    CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66575

    摘要： A semiconductor device includes a substrate, a multilayered assembly of high k dielectric materials formed on the substrate, and a first conducting material formed on the upper layer of the assembly of high k dielectric materials. The multilayered high k dielectric assembly includes a lower layer, an upper layer, and a diffusion barrier layer formed between the lower and upper dielectric layers. The diffusion barrier layer has a greater affinity for oxygen than the upper and lower layers. The first conducting layer includes a conducting compound of at least a metal element and oxygen.

    摘要翻译： 半导体器件包括衬底，形成在衬底上的高k电介质材料的多层组件和形成在高k电介质材料的组件的上层上的第一导电材料。 多层高k电介质组件包括下层，上层和形成在下介电层和上电介质层之间的扩散阻挡层。 扩散阻挡层与上层和下层具有比氧更大的亲和性。 第一导电层包括至少金属元素和氧的导电化合物。

    MOS device with nano-crystal gate structure
    2.
    发明申请
    MOS device with nano-crystal gate structure 有权
    具有纳米晶体栅结构的MOS器件

    公开(公告)号：US20070176227A1

    公开(公告)日：2007-08-02

    申请号：US11343624

    申请日：2006-01-30

    申请人： Chun-Li Liu ,  Tushar Merchant ,  Marius Orlowski ,  Matthew Stoker

    发明人： Chun-Li Liu ,  Tushar Merchant ,  Marius Orlowski ,  Matthew Stoker

    IPC分类号： H01L29/792 ,  H01L21/8238

    CPC分类号： H01L29/7883 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/78

    摘要： Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.

    摘要翻译： 为非易失性半导体器件提供了方法和装置。 该装置包括其中具有源极区域和漏极区域的衬底，漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。 栅极结构包括：基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层和覆盖一个以上杂质阻挡层的栅极导体层 。 最靠近栅极导体的阻挡层也可用于调节器件的阈值电压和/或从栅极导体层延迟掺杂剂扩散。

    SOI template layer
    3.
    发明申请
    SOI template layer 有权
    SOI模板层

    公开(公告)号：US20050070056A1

    公开(公告)日：2005-03-31

    申请号：US10670928

    申请日：2003-09-25

    申请人： Chun-Li Liu ,  Marius Orlowski ,  Matthew Stoker ,  Philip Tobin ,  Mariam Sadaka ,  Alexander Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Shawn Thomas ,  Ted White

    发明人： Chun-Li Liu ,  Marius Orlowski ,  Matthew Stoker ,  Philip Tobin ,  Mariam Sadaka ,  Alexander Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Shawn Thomas ,  Ted White

    IPC分类号： H01L20060101 ,  H01L21/00 ,  H01L21/338

    CPC分类号： H01L29/161 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/1054 ,  Y10S438/933

    摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.

    摘要翻译： 用于在SOI衬底的模板层材料中注入空位的空位注入工艺。 模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。 然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。 进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。 一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。 空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

    MOS device with multi-layer gate stack
    4.
    发明申请
    MOS device with multi-layer gate stack 有权
    具有多层栅极堆叠的MOS器件

    公开(公告)号：US20070176247A1

    公开(公告)日：2007-08-02

    申请号：US11343623

    申请日：2006-01-30

    申请人： Chun-Li Liu ,  Marius Orlowski ,  Matthew Stoker

    发明人： Chun-Li Liu ,  Marius Orlowski ,  Matthew Stoker

    IPC分类号： H01L29/94

    CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    摘要： Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.

    摘要翻译： 为半导体器件提供了方法和装置。 该装置包括其中具有源极区和漏极区的衬底，漏极区被延伸到衬底的第一表面的沟道区分离，以及位于沟道区上方的多层栅极结构。 栅极结构包括：栅极电介质，优选地与沟道区基本上接触的Hf，Zr或HfZr的氧化物，例如覆盖栅极电介质的MoSi的氧化物的第一导体层， 例如多晶硅，覆盖在第一导体层上并且适于向沟道区施加电场，以及位于第一导体层上方或下方的杂质迁移抑制层（例如MoSi），并适于抑制移动 杂质，例如氧气，朝向衬底。

    Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
    5.
    发明申请
    Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权
    采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺

    公开(公告)号：US20060166492A1

    公开(公告)日：2006-07-27

    申请号：US11043577

    申请日：2005-01-26

    申请人： Marius Orlowski ,  Vance Adams ,  Chun-Li Liu ,  Matthew Stoker

    发明人： Marius Orlowski ,  Vance Adams ,  Chun-Li Liu ,  Matthew Stoker

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/66545 ,  H01L21/28061 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

    摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.

    摘要翻译： 半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。 第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。

    Method of forming nanoclusters
    6.
    发明申请
    Method of forming nanoclusters 审中-公开
    形成纳米团簇的方法

    公开(公告)号：US20060189079A1

    公开(公告)日：2006-08-24

    申请号：US11065519

    申请日：2005-02-24

    申请人： Tushar Merchant ,  Ramachandran Muralidhar ,  Rajesh Rao ,  Matthew Stoker ,  Sherry Straub

    发明人： Tushar Merchant ,  Ramachandran Muralidhar ,  Rajesh Rao ,  Matthew Stoker ,  Sherry Straub

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/66825

    摘要： A method for forming nanoclusters includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate, exposing the semiconductor substrate to a first flux of atoms to form first nuclei on the dielectric layer, exposing the first nuclei to a first inert atmosphere after exposing the semiconductor substrate to the first flux, and exposing the semiconductor substrate to a second flux of atoms to form second nuclei after exposing the first nuclei to an inert atmosphere.

    摘要翻译： 一种形成纳米团簇的方法包括提供半导体衬底; 在所述半导体衬底上形成电介质层，将所述半导体衬底暴露于所述第一原子通量，以在所述电介质层上形成第一核，在将所述半导体衬底暴露于所述第一焊剂之后，将所述第一核暴露于第一惰性气氛， 半导体衬底到第二个原子通量，以在将第一核暴露于惰性气氛之后形成第二核。