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67 条记录 (耗时 0.027 秒)

    Avoiding plasma charging in integrated circuits
    1.
    发明授权
    Avoiding plasma charging in integrated circuits 有权
    避免集成电路中的等离子体充电

    公开(公告)号：US07846800B2

    公开(公告)日：2010-12-07

    申请号：US12043148

    申请日：2008-03-06

    申请人： Chung Foong Tan ,  Jae Gon Lee ,  Lee Wee Teo ,  Elgin Quek ,  Chunshan Yin

    发明人： Chung Foong Tan ,  Jae Gon Lee ,  Lee Wee Teo ,  Elgin Quek ,  Chunshan Yin

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823857 ,  H01L27/0251 ,  H01L27/092

    摘要： A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection control terminal is coupled to the primary circuit. The protection circuit includes a protection gate oxide of a second thickness T2 which is less than T1. The protection gate oxide reduces plasma induced damage in the primary circuit.

    摘要翻译： 提供具有电路控制端子，初级电路和保护电路的电路。 初级电路包括厚度T1的初级控制端子和主栅极氧化物。 主控制端子耦合到电路控制端子。 具有保护控制端子的保护电路耦合到初级电路。 保护电路包括小于T1的第二厚度T2的保护栅极氧化物。 保护栅极氧化物减少了初级电路中的等离子体引起的损坏。

    Novel methods to reduce gate contact resistance for AC reff reduction
    7.
    发明申请
    Novel methods to reduce gate contact resistance for AC reff reduction 有权
    降低栅极接触电阻的新方法

    公开(公告)号：US20120038009A1

    公开(公告)日：2012-02-16

    申请号：US12806354

    申请日：2010-08-11

    申请人： Eng Huat Toh ,  Elgin Quek ,  Chunshan Yin ,  Chung Foong Tan ,  Jae Gon Lee

    发明人： Eng Huat Toh ,  Elgin Quek ,  Chunshan Yin ,  Chung Foong Tan ,  Jae Gon Lee

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

    摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.

    摘要翻译： 制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。 在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。 执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。 这导致较低的栅极接触电阻并有效降低器件的AC Reff。

    Methods to reduce gate contact resistance for AC reff reduction
    8.
    发明授权
    Methods to reduce gate contact resistance for AC reff reduction 有权
    减少AC降低栅极接触电阻的方法

    公开(公告)号：US08674457B2

    公开(公告)日：2014-03-18

    申请号：US12806354

    申请日：2010-08-11

    申请人： Eng Huat Toh ,  Elgin Quek ,  Chunshan Yin ,  Chung Foong Tan ,  Jae Gon Lee

    发明人： Eng Huat Toh ,  Elgin Quek ,  Chunshan Yin ,  Chung Foong Tan ,  Jae Gon Lee

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

    摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.

    摘要翻译： 制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。 在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。 执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。 这导致较低的栅极接触电阻并有效降低器件的AC Reff。