公开(公告)号：US20110156121A1

公开(公告)日：2011-06-30

申请号：US12650561

申请日：2009-12-31

申请人： Lee Wee Teo ,  Chunshan Yin ,  Shyue Seng Tan ,  Chüng Foong Tan ,  Jae Gon Lee ,  Elgin Quek ,  Purakh Raj Verma

发明人： Lee Wee Teo ,  Chunshan Yin ,  Shyue Seng Tan ,  Chüng Foong Tan ,  Jae Gon Lee ,  Elgin Quek ,  Purakh Raj Verma

IPC分类号： H01L29/423 ,  H01L21/302 ,  H01L21/28

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/11521

摘要： A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.

摘要翻译： 提出了一种形成装置的方法。 提供了具有具有第一和第二相邻表面的特征的基底。 器件层形成在特征的第一和第二相邻表面上。 第一相邻表面上的器件层的第一部分包括纳米晶体，而第二相邻表面上的器件层的第二部分没有纳米晶体。

公开(公告)号：US08530310B2

公开(公告)日：2013-09-10

申请号：US12650561

申请日：2009-12-31

申请人： Lee Wee Teo ,  Chunshan Yin ,  Shyue Seng Tan ,  Chung Foong Tan ,  Jae Gon Lee ,  Elgin Quek ,  Purakh Raj Verma

发明人： Lee Wee Teo ,  Chunshan Yin ,  Shyue Seng Tan ,  Chung Foong Tan ,  Jae Gon Lee ,  Elgin Quek ,  Purakh Raj Verma

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/11521

摘要： A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.

摘要翻译： 提出了一种形成装置的方法。 提供了具有具有第一和第二相邻表面的特征的基底。 器件层形成在特征的第一和第二相邻表面上。 第一相邻表面上的器件层的第一部分包括纳米晶体，而第二相邻表面上的器件层的第二部分没有纳米晶体。

公开(公告)号：US07935589B2

公开(公告)日：2011-05-03

申请号：US12111214

申请日：2008-04-29

申请人： Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan ,  Elgin Quek

发明人： Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan ,  Elgin Quek

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： A transistor disposed on a substrate includes a gate, spacers on gate sidewalls, and diffusion regions adjacent to the gate. Silicide contacts on the diffusion regions are displaced from the spacers by a distance G. Stressors may be provided in the diffusion region to induce a first stress in the channel region of the transistor.

摘要翻译： 设置在基板上的晶体管包括栅极，栅极侧壁上的间隔物和与栅极相邻的扩散区域。 扩散区上的硅化物接触从间隔物移位距离G。可以在扩散区域中提供应激源以在晶体管的沟道区域中引起第一应力。

公开(公告)号：US20100304556A1

公开(公告)日：2010-12-02

申请号：US12471803

申请日：2009-05-26

申请人： Chunshan Yin ,  Jae Gon Lee ,  Shyue Seng Tan ,  Elgin Kiok Boone Quek ,  Chung Foong Tan ,  Lee Wee Teo

发明人： Chunshan Yin ,  Jae Gon Lee ,  Shyue Seng Tan ,  Elgin Kiok Boone Quek ,  Chung Foong Tan ,  Lee Wee Teo

IPC分类号： H01L21/28

CPC分类号： H01L29/42332 ,  H01L29/42328 ,  H01L29/7881

摘要： A method of manufacture of an integrated circuit system includes: providing a mesa over a substrate; forming a trench in the substrate adjacent the mesa; forming a second gate and a charge storage material along a trench sidewall; and forming a first gate from the mesa.

摘要翻译： 一种制造集成电路系统的方法，包括：在衬底上提供台面; 在邻近台面的衬底中形成沟槽; 沿着沟槽侧壁形成第二栅极和电荷存储材料; 并从台面形成第一个门。

公开(公告)号：US08446779B2

公开(公告)日：2013-05-21

申请号：US12583486

申请日：2009-08-21

申请人： Elgin Quek ,  Chunshan Yin ,  Shyue Seng Tan ,  Jae Gon Lee ,  Chung Foong Tan

发明人： Elgin Quek ,  Chunshan Yin ,  Shyue Seng Tan ,  Jae Gon Lee ,  Chung Foong Tan

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L29/42324 ,  G11C16/0416 ,  G11C2216/06 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42332

摘要： A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.

摘要翻译： 非易失性存储器件包括具有金字塔形的硅纳米晶体作为电子存储元件的浮动栅极。 电子从金字塔形的硅纳米晶体通过栅极氧化层隧穿到非易失性存储器件的控制栅极。 每个硅纳米晶体的锥体形状在其峰值处集中电场以促进电子隧穿。 这允许擦除过程发生在比现有技术的器件更低的隧道电压和更短的隧道时间。

公开(公告)号：US20110044115A1

公开(公告)日：2011-02-24

申请号：US12583486

申请日：2009-08-21

申请人： Elgin Quek ,  Chunshan Yin ,  Shyue Seng Tan ,  Jae Gon Lee ,  Chung Foong Tan

发明人： Elgin Quek ,  Chunshan Yin ,  Shyue Seng Tan ,  Jae Gon Lee ,  Chung Foong Tan

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L29/42324 ,  G11C16/0416 ,  G11C2216/06 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42332

摘要： A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.

摘要翻译： 非易失性存储器件包括具有金字塔形的硅纳米晶体作为电子存储元件的浮动栅极。 电子从金字塔形的硅纳米晶体通过栅极氧化层隧穿到非易失性存储器件的控制栅极。 每个硅纳米晶体的锥体形状在其峰值处集中电场以促进电子隧穿。 这允许擦除过程发生在比现有技术的器件更低的隧道电压和更短的隧道时间。

公开(公告)号：US07998835B2

公开(公告)日：2011-08-16

申请号：US12008841

申请日：2008-01-15

申请人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

发明人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L29/165 ,  H01L21/76254 ,  H01L29/1054 ,  Y10S438/933

摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.

摘要翻译： 描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。 施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。 绝缘体邻近最外层应变硅层设置。 最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。 处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。 处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。 重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

公开(公告)号：US08324031B2

公开(公告)日：2012-12-04

申请号：US12144652

申请日：2008-06-24

申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Yung Fu Chong ,  Elgin Quek ,  Sanford Chu

发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Yung Fu Chong ,  Elgin Quek ,  Sanford Chu

IPC分类号： H01L21/00

CPC分类号： H01L29/66537 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/3223 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/532 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

摘要翻译： 提出了一种形成装置的方法。 该方法包括提供具有第一和第二区域的结构。 在第一和第二区域的至少一部分之间形成扩散阻挡层。 扩散屏障包括减少元件在第一和第二区域之间的扩散的空腔。

公开(公告)号：US20110278645A1

公开(公告)日：2011-11-17

申请号：US13191288

申请日：2011-07-26

申请人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

发明人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

IPC分类号： H01L29/165

CPC分类号： H01L29/165 ,  H01L21/76254 ,  H01L29/1054 ,  Y10S438/933

摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.

摘要翻译： 描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。 施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。 绝缘体邻近最外层应变硅层设置。 最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。 处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。 处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。 重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

公开(公告)号：US20090179226A1

公开(公告)日：2009-07-16

申请号：US12008841

申请日：2008-01-15

申请人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

发明人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

IPC分类号： H01L21/30 ,  H01L29/12

CPC分类号： H01L29/165 ,  H01L21/76254 ,  H01L29/1054 ,  Y10S438/933

摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.

摘要翻译： 描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。 施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。 绝缘体邻近最外层应变硅层设置。 最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。 处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。 处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。 重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。